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intel? server board S3000PT technical product specification d69383 - 00 4 revision 1. 3 february 2007 enterprise platforms and services division free datasheet http://
revision history intel? server board S3000PT tps ii revision 1.3 revision history date revision number modifications september 2006 1.0 initial r elease december , 2006 1 .1 updated february, 2007 1.2 updated calculated mtbf data february, 2007 1.3 inserted non - standard connector information matrix and table disclaimers information in this document is provided in connection with intel ? products. no license, express, imp lied, by estoppel, or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implie d warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instruct ions marked reserved or undefined. intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. this document contains information on products in the design p hase of development. do not finalize a design with this information. revised information will be published when the product is available. verify with your local sales office that you have the latest datasheet before finalizing a design. the intel? server board s30 00pt may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. intel, pentium?, itanium, and xeon are trademarks or registered trademarks of intel corporation. *other brands and names may be claimed as the property of others. copyright ? intel corporation 2006. free datasheet http://
intel? server board S3000PT tps table of contents revision 1.3 iii table of contents 1. introduction ................................ ................................ ................................ ........................ 1 1.1 section outline ................................ ................................ ................................ ....... 1 1.2 server board use disclaimer ................................ ................................ ................. 1 2. server board overview ................................ ................................ ................................ ...... 2 2.1 intel? server board S3000PT feature set ................................ ............................ 2 3. functional architecture ................................ ................................ ................................ ..... 6 3.1 processor sub - system ................................ ................................ ........................... 7 3.1.1 processor voltage regulator down (vrd) ................................ ............................. 7 3.1.2 reset configuration logic ................................ ................................ ...................... 8 3.1.3 processor support ................................ ................................ ................................ . 8 3.2 intel ? 3000 chipset ................................ ................................ ................................ . 9 3.2.1 memory controller hub (mch) ................................ ................................ ............... 9 3.2.2 i/o controller hub ................................ ................................ ................................ 11 3.3 memory su b - system ................................ ................................ ............................ 13 3.3.1 memory dimm support ................................ ................................ ........................ 15 3.4 i/o sub - system ................................ ................................ ................................ .... 15 3.4.1 pci subsystem ................................ ................................ ................................ .... 15 3.4.2 interrupt routing ................................ ................................ ................................ .. 16 3.5 pci error handling ................................ ................................ ............................... 18 3.5.1 video support ................................ ................................ ................................ ...... 21 3.5.2 network interface controller (nic) ................................ ................................ ....... 21 3.5.3 super i/o chip ................................ ................................ ................................ ..... 22 3.5.4 bios f lash ................................ ................................ ................................ ........... 23 3.5.5 system health support ................................ ................................ ........................ 24 3.6 replacing the back - up battery ................................ ................................ ............ 24 4. system bios ................................ ................................ ................................ ..................... 25 4.1 bios identification string ................................ ................................ ..................... 25 4.2 logo / diagnostic window ................................ ................................ .................... 25 4.3 bios setup utility ................................ ................................ ................................ 26 4.3.1 operation ................................ ................................ ................................ ............. 26 4.3.2 server platform setup screens ................................ ................................ ............ 28 free datasheet http://
table of contents intel? server board S3000PT tps iv revision 1.3 4.4 loading bios defaults ................................ ................................ ........................ 49 5. platform management architecture ................................ ................................ ................ 50 5.1 console redirection ................................ ................................ ............................. 50 5.1.1 serial configuration settings ................................ ................................ ................ 50 5.1.2 keystroke mappings ................................ ................................ ............................. 50 5.1.3 limitations ................................ ................................ ................................ ............ 51 5.2 intel ? active management technology (amt) ................................ ...................... 51 5.3 wired for management (wfm) ................................ ................................ ........... 53 5.3. 1 pxe bios support ................................ ................................ ............................... 53 5.4 system management bios (smbios) ................................ ................................ . 53 5.5 security ................................ ................................ ................................ ................ 53 5.5.1 operating model ................................ ................................ ................................ ... 53 5.5.2 password protection ................................ ................................ ............................ 54 5.5.3 password clear ................................ ................................ ................................ .... 54 6. error reporting and handling ................................ ................................ ......................... 55 6.1 error handling and logging ................................ ................................ ................. 55 6.1.1 error sources and types ................................ ................................ ..................... 55 6.1.2 error logging via smi handler ................................ ................................ ............. 56 6.1.3 smbios type 15 ................................ ................................ ................................ . 56 6.1.4 logging format conventions ................................ ................................ ............... 56 6.2 error messages and error codes ................................ ................................ ......... 58 6.2.1 diagnostic leds ................................ ................................ ................................ ... 58 6.2.2 post code checkpoints ................................ ................................ ..................... 60 6.2.3 post error messages and handling ................................ ................................ ... 62 6.2.4 post error beep codes ................................ ................................ ...................... 63 6.2.5 post error pause option ................................ ................................ .................... 63 7. connectors and jumper blocks ................................ ................................ ...................... 64 7.1 power connectors ................................ ................................ ................................ 64 7.2 smbus header ................................ ................................ ................................ ..... 64 7.3 front panel connector ................................ ................................ ......................... 65 7.4 i/o connectors ................................ ................................ ................................ ..... 65 7.4.1 vga connector ................................ ................................ ................................ .... 65 7.4.2 nic connectors ................................ ................................ ................................ .... 66 7.4.3 sata connectors ................................ ................................ ................................ 66 free datasheet http://
intel? server board S3000PT tps table of contents revision 1.3 v 7.4.4 serial port connectors ................................ ................................ ......................... 67 7.4.5 usb connector ................................ ................................ ................................ .... 67 7.5 fan headers ................................ ................................ ................................ ........ 68 7.6 miscellaneous headers and connectors ................................ .............................. 69 7.6.1 back panel i/o connectors ................................ ................................ .................. 69 7.6.2 non - standard connector information matrix ................................ ........................ 69 7.6.3 post code leds ................................ ................................ ................................ 70 7.7 jumper blocks ................................ ................................ ................................ ..... 70 8. absolute maximum r atings ................................ ................................ ............................. 72 8.1 mean time between failures (mtbf) test results ................................ ............. 72 9. design and environmental specifications ................................ ................................ ..... 73 9.1 p ower budget ................................ ................................ ................................ ...... 73 9.2 pr oduct regulatory compliance ................................ ................................ ........... 73 9.2.1 product safety compliance ................................ ................................ .................. 73 9.2.2 product emc compliance C class a compliance ................................ ................ 74 9.2.3 certifications / registrations / declarat ions ................................ .......................... 74 9.2.4 product regulatory compliance markings ................................ ........................... 75 9.3 electromagnetic compatibility notices ................................ ................................ . 75 9.3.1 industry canada (ices - 003 ) ................................ ................................ ................ 75 9.3.2 europe (ce declaration of conformity) ................................ ................................ 76 9.3.3 australia / new zealand ................................ ................................ ....................... 76 9.4 restriction of hazardous substances (rohs) ................................ ...................... 76 9.5 calculated mean time between fa ilures (mtbf) ................................ ................ 76 9.6 mechanical specifications ................................ ................................ .................... 77 10. hardware monitoring ................................ ................................ ................................ ....... 78 10.1 monitored components ................................ ................................ ........................ 78 10.1.1 fan speed control ................................ ................................ ............................... 79 glossary ................................ ................................ ................................ ................................ .. 80 references ................................ ................................ ................................ .............................. 83 free datasheet http://
list of figures intel? server board S3000PT tps vi revision 1.3 list of figures figure 1. intel ? server board S3000PT layout ................................ ................................ .......... 4 figure 2 . intel ? server boar d S3000PT block diagram ................................ .............................. 6 figure 3. memory bank label definition ................................ ................................ ................... 14 figure 4. interrupt routing diagram ................................ ................................ .......................... 19 figure 5. intel? ich7r controller interrupt routing diagram ................................ ................... 20 figure 6. setup utility main screen display ................................ ................................ .......... 29 figure 7. setup utility advanced screen display ................................ ................................ .. 30 figure 8. setup utility processor configuration screen dis play ................................ ........... 31 figure 9. setup utility memory configuration screen display ................................ ............... 32 figure 10. setup utility sata controller configuration screen display ................................ 33 figure 11. setup u tility serial port configuration screen display ................................ ......... 35 figure 12. setup utility usb controller configuration screen display ................................ .. 36 figure 13. setup utility pci configuration screen display ................................ ................... 37 figure 14. setup utility power screen display ................................ ................................ ..... 38 figure 15. setup utility boot configuration screen display ................................ .................. 38 figure 16. setup utility hardware health configuration screen display ............................... 39 figure 17. setup utility hardware monitor screen display ................................ ................... 40 figure 18. setup utility security configuration screen display ................................ ............. 41 figure 19. setup u tility server management configuration screen display ......................... 42 figure 20. setup utility console redirection screen display ................................ ................ 44 figure 21. setup utility server management system information screen d isplay ................ 45 figure 22. setup utility boot options display ................................ ................................ ....... 46 figure 23. setup utility boot options display ................................ ................................ ....... 46 figure 24. setup utility error manager screen displa y ................................ ......................... 47 figure 25. setup utility exit screen display ................................ ................................ .......... 48 figure 26. location of diagnostic leds on server board ................................ ......................... 59 figure 27. back panel i/o connections (not to scale) ................................ ............................... 69 figure 28 . intel? server board S3000PT mechanical drawing ................................ ................. 77 figure 29. fan speed control block diagram ................................ ................................ ........... 79 free datasheet http://
intel? server board S3000PT tps list of tables revision 1.3 vii list of tables table 1. server board layout reference ................................ ................................ .................... 5 table 2. processor support matrix ................................ ................................ .............................. 8 table 3. segment e connections ................................ ................................ ............................. 10 table 4. supported ddr 2 module s ................................ ................................ .......................... 10 table 5. me mory bank labels and dimm population order ................................ ...................... 14 table 6. characteristics of dual/single channel configuration with or without dynamic mode . 15 table 7. segment a configuration ids ................................ ................................ ...................... 16 table 8. segment a arbitration connections ................................ ................................ ............ 16 table 9. pci interrupt routing/sharing ................................ ................................ ..................... 17 table 10. interrupt definitions ................................ ................................ ................................ ... 17 table 11. video modes ................................ ................................ ................................ ............. 21 table 12. intel? 82573e interface connector ( nic1) ................................ ................................ 22 table 13. intel? 82573 v interface connector (nic2) ................................ ................................ 22 table 14. serial a header pin - out ................................ ................................ ............................. 23 table 15. serial b header pin - out ................................ ................................ ............................. 23 table 16. bios setup page layout ................................ ................................ .......................... 26 table 17. bios setup: keyboard command bar ................................ ................................ ...... 27 table 18. setup utility main screen fiel ds ................................ ................................ ........... 29 table 19. setup utility processor configuration screen fields ................................ ............. 31 table 20. setup utility memory configuration screen fields ................................ ................ 33 table 21. setup utility ata controller configuration screen fields ................................ ..... 34 table 22. setup utility serial ports configuration screen fields ................................ .......... 35 table 23. setup utility usb controller configuration screen fields ................................ ..... 36 table 24. setup utility pci configuration screen fields ................................ ....................... 37 table 25. setup utility power screen fields boot configuration ................................ ........... 38 table 26. setup utility system acoustic and per formance configuration screen fields ...... 39 table 27. setup utility security configuration screen fields ................................ ................ 41 table 28. setup utility server management configuration screen fields ............................. 42 table 29. setup utility console redirection configuration fields ................................ ......... 44 table 30. setup utility server management system information fields ............................... 45 table 31. setup utility error manage r screen fields ................................ ............................ 46 free datasheet http://
list of t ables intel? server board S3000PT tps viii revision 1.3 table 32. setup utility error manager screen fields ................................ ........................... 47 table 33. setup utility error manager screen fields ................................ ............................ 47 table 34. setup utility exit sc reen fields ................................ ................................ ............. 48 table 35 . console redirection escape sequences for headless operation ............................. 51 table 36 . function list ................................ ................................ ................................ .............. 53 table 37 . security features operating model ................................ ................................ ........... 54 table 38. event list ................................ ................................ ................................ .................. 55 table 39. smbios type 15 event record format ................................ ................................ .... 57 table 40. event type definition table ................................ ................................ ...................... 57 table 41. post progress cod e led example ................................ ................................ ......... 59 table 42 . post code checkpoints ................................ ................................ .......................... 60 table 43 . post error messages and handling ................................ ................................ ........ 63 table 44 . post error beep codes ................................ ................................ ........................... 63 tab le 45. power connector pin - out ( j3k2 ) ................................ ................................ ............... 64 table 46. smbus header pin - out ( j1a1 ) ................................ ................................ .................. 64 table 47. front panel 14 - pin header pin - out ( j4k3 ) ................................ ................................ 65 table 48. vga connector pin - ou t ( j4a1 ) ................................ ................................ ................. 65 table 49. nic1 - intel? 82573e (10/100/1000) connector pin - out ( ja2a1 ) ............................... 66 table 50. nic2 - intel? 82 573v (10/100/1000) connector pin - out ( ja2a2 ) ............................... 66 table 51 . sata connector pin - out ( j1c2, j1c3 ) ................................ ................................ ..... 66 table 52. external db9 serial a port pin - out (j 3 a1) ................................ ................................ 67 table 53. internal 9 - pin serial b port pin - out ( j2b1 ) ................................ ................................ . 67 table 54. usb connectors pin - out ( ja2a1 ) ................................ ................................ ............. 67 table 55. optional usb connection header pin - out ( j1c1 ) ................................ ..................... 68 table 56. 8 - pin fan headers pin - out ( j 3k1,j4k2,j4k1 ) ................................ .......................... 68 table 57. non - stand ard connector information ................................ ................................ ........ 70 table 58. cmos clear jumper options ( j1b1) ................................ ................................ ........ 70 table 59. nic1 firmware update jumper options ( j1b 2 ) ................................ ........................ 71 table 60. system maintenance mode jumper options ( j1b 3 ) ................................ ................. 71 table 61. absolute maximum ratings ................................ ................................ ....................... 72 table 62. the board power budget ................................ ................................ .......................... 73 table 63. product certification markings ................................ ................................ .................. 75 table 64. calculated mtbf data ................................ ................................ .............................. 76 table 65. monitored components ................................ ................................ ............................. 78 free datasheet http://
intel? server board S3000PT tps introduction revision 1.3 1 1. introduction this intel? server board S3000PT technical product specification (tps) provides a high - level technical d escription for the intel? server board S3000PT . it details the architecture and feature set for all functional sub - systems that make up the server board. 1.1 section outline this document is divided into the following chapters: e section 1 C introduction e section 2 C server board overview e section 3 C functional architecture e section 4 C system bios e section 5 C platform management architecture e sectio n 6 C error reporting and handling e section 7 C connectors and jumper blocks e section 8 C absolute maximum ratings e section 9 C design and environmental specifications e section 10 C hardware monitoring e glossary e references 1.2 server board use disclaimer intel? server boards contain a number of high - density vlsi* and power delivery components that need adequate airflow to cool. intels own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together. it is the responsibility of the system integrator that chooses not to use intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions. intel corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of its published operating or non - operating limits. free datasheet http://
server board overview intel? server board s3000 pt tps 2 revision 1.3 2. server board overview the intel? server board S3000PT is a monolithic printed circuit board with features that support the up server market . 2.1 intel? server board S3000PT feature set the intel? server board s3 000pt supports the following feature set: e processor and front side bus (fsb) support - supports intel? xeon? processor 3000 sequence, intel? core?2 extreme edition, intel? core?2 duo, intel? pentium? processor extreme edition,intel? pentium? d processor,int el? pentium? 4 processor, intel? celeron? d processor in the intel? lga775 package - supports intel? dual core architecture - supports hyper - threading technology - supports intel? extended memory system 64 technology (intel? em64t) e intel? 3000 chipset components - intel? 3000 mch memory controller hub - intel? ich7r i/o controller - 12 - deep in - order queue e memory system - four dimm sockets supporting ddr2 533/667mhz dimms - data bandwidth per channel of 4.2gb/s or 8.4gb/s in dual channel when using ddr2 667mhz - support for up to two ddr2 channels for a total of four dimms (2 dimms / c hannel) providing up to 8 - gb max memory capacity. - support for 512 - mb, 1 - gb and 2 - gb dram modules e i/o subsystem e board i/o subsystem: - segment a: o ne embedded ati * es1000 video controller ( suppor ts pci specification, rev 2.3 ) . - segment b : one x1 pci express* resource implemented as an embedded intel? 82573 v 10/100/1000 g igabit ethernet controller - segment c: one x1 pci express * resource implemented as an embedded intel? 82573 e 10/100/1000 g igabit ethernet controller - segment d : one x8 pci express* resource implemented as a riser slot supporting single x1/x4/x8 pci express* add - in cards through a riser e serial ata host controller e two independent sata ports suppo rt data transfer rates up to 3.0 gb/s ( 300 mb/s) per port e universal serial bus 2.0 (usb) free datasheet http://
intel? server board S3000PT tps server board overview revision 1.3 3 e two external usb ports with an additional internal header providing two optional usb ports for front panel support. - supports wake - up from sleeping states s1 - s4 (s3 not supported) - supports legacy keyboard/m o use connections when using ps / 2 - usb dongle e lpc (low pin count) bus segment with one embedded device - super i/o controller chips providing all pc - compatible i/o ( two serial com port s ) and integrated hardware monitoring - lc super i/o = sm s c* sch5027 or smsc* s ch50 1 7 e customized 14 - pin ssi front panel 2x9 power connectors e fan s upport - three customized 8 - pin fan header s with pwm and tach capability - one 4 - pin fan header without pwm and tach capability e intel? light - guided diagnostic leds to display post code indicato rs during boot free datasheet http://
server board overview intel? server board S3000PT tps 4 revision 1.3 the following figure shows the board layout of the intel? server board S3000PT . each connector and major component is identified by letter and is identified in table 1. figure 1 . intel ? server board S3000PT layout free datasheet http://
intel? server board S3000PT tps server board overview revision 1.3 5 table 1 . server board layout reference ref description ref description a post leds s battery b pci - e x8 riser slot t usb 3 and 4 header c bios flash(spi) u sata port 2 d intel? 82802 ich7r v sata port 1 e clock generator w serial b header f smsc* sch5027 or smsc* sch5017 super i/o ( sio ) x video memory g intel ? 3000 memory controller hub ( mch ) y intel? 82573e lan controller h 775 - land (lga) cpu socket z intel? amt firmware ( nic1) update jumper i system fan 1 (8 - pin) aa clear cmos jumper j system fan 2 (8 - pin) bb nic1 spi flash k system fan 3 (8 - pin) cc intel? 825 73v lan controller l 2 x 7 front panel header dd smbus connector m 2 x 9 power connector ee nic1 rj - 45 and usb 1 and 2 connector n aux iliary fan (4 - pin) ff nic2 rj - 45 connector o memory slot dimm 2b gg nic2 spi eeprom p memory slot dimm 1b hh serial a connector q memory slot dimm 2a jj vga connector r memory slot dimm 1a kk ati* es1000 video controller free datasheet http://
functional architecture intel? server board S3000PT tps 6 revision 1.3 3. functional architec ture this section provides a high - level description of the functionality associated with the architectural blocks that make up the intel? server board S3000PT . figure 2 . intel ? server board S3000PT block diagram free datasheet http://
intel? server board S3000PT tps functional architecture revision 1.3 7 3.1 processor sub - s ystem the intel? server board S3000PT supports the following: e intel? xeon? processor 3000 sequence e intel? core?2 extreme edition e intel? core?2 duo e intel? pentium? p rocessor extreme edition e intel? pentium? d processor e intel? pentium? 4 processor e intel? celeron? d processor the processors , built on 90nm and 65nm process technology in the 775 - land packa ge , utilize flip - chip land grid arr ay (fc - lga4) package technology and plug into a 775 - land lga socket ( which is referred to as the intel ? lga775 socket ) . the processors in the 775 - land package, like their predecessors in the 478 - pin package, are based on the same pentium? 4 micro - architecture. they maintain compatibility with 32 - bit software written for the ia - 32 instruction set, while supporting 64 - bit native mode operation when coupled with supported 64 - bit operating systems and applications. the celeron ? processor is not available with dual core, hyper - t h reading technology or intel? em64t. 3.1.1 processor voltage regulator down (vrd) the intel ? server board s3000 pt has a vrd (voltage regulator down) to support one processor. it is compliant with the vr d 1 1 d c - dc converter design guide line and provides a maximum of 12 5 a, which is capable of supporting the requirements for the following processors: e intel? xeon? processor 3000 sequence e intel? core?2 extreme edition e intel? core?2 duo e intel? pentium? processor extreme edition e intel? pentium? d processor e intel? pentium? 4 processor e intel? celeron? d processor the board hardware monitors the processor v tten (output enable for vtt) pin bef ore turning on the vrd. if the vtten pin of the processors is not asserted , the power on logic will not turn on the vrd. free datasheet http://
functional architecture intel? server board S3000PT tps 8 revision 1.3 3.1.2 reset configuration logic the bios determines the processor stepping, cache size, etc., through the cpuid instruction. the processor in formation is read at every system power - on. note: the processor speed is the processor power - on reset default value. no manual processor speed setting options exist either in the form of a bios setup option or jumpers. 3.1.3 processor support the intel ? server board s3000 pt supports one processor in the intel ? lga775 package. the support circuitry on the server board consists of the following: e one intel ? lga775 processor socket supporting: o intel? xeon? processor 3000 sequence o intel? core?2 extreme edition proces sor o intel? core?2 duo processor o intel? pentium? processor extreme edition processor o intel? pentium? d p rocessor o intel? pentium? 4 p rocessor o intel? celeron? d p rocessor e processor host bus agtl+ support circuitry. table 2 . processor support matrix process or name sock et core frequency cache size fsb frequency intel? xeon ? 3000 processor intel ? lga775 4mb l2 800/1066mhz intel? xeon ? 3000 processor intel ? lga775 2mb l2 800/1066mhz intel? core?2 extreme edition intel ? lga775 2.93gh z 4mb l2 1066mhz intel? core?2 duo intel ? lga775 intel? pentium ? 4 processor extreme edition intel ? lga775 3.2ghz 2 x 1mb l2 800mhz intel? pentium ? 4 processor extreme edition intel ? lga775 3.73ghz 2mb l2 1066mhz intel? pentium? d intel ? lga775 3.2 C 4.0ghz 2 x 1mb l2 800mhz intel? pentium? 4 intel ? lga775 3.2 C 4.0ghz 1mb or 2mb l2 800mhz intel? celeron? d intel ? lga775 2.26 C 3.2 ghz 256k l2 533mhz free datasheet http://
intel? server board S3000PT tps functional architecture revision 1.3 9 note : for a complete list of all supported processors, please visit the intel? server board s3000 p t support site located at the following url: http://support.intel.com/support/motherboards/server/S3000PT/ in a ddition to the circuitry described above, the processor subsystem contains the following: e reset configuration logic 3.2 intel ? 3000 chipset the intel? server board S3000PT is designed around the intel? 3000 c hipset. the chipset provides an integrated i/o bridg e and memory controller, and a flexible i/o subsystem core ( pci express * ) . the chipset consi sts of three primary components. 3.2.1 memory controller hub (mch) 3.2.1.1 intel? 3000 chipset mch: memory control hub the mch accepts access requests from the host (processor) b us and directs those accesses to memory or to one of the pci express or pci buses. the mch monitors the host bus, examining addresses for each request. accesses may be directed to the following: e a memory request queue for subsequent forwarding to the memor y subsystem e an outbound request queue for subsequent forwarding to one of the pci express or pci buses the mch also accepts inbound requests from t he intel? ich7r . the mch is responsible for generating the appropriate controls to control data transfer to a nd from memory. the mch is a 1202 - ball fc - bga device and uses the proven components of the following previous generations: e pentium? p rocessor extreme edition , pentium? d processor , pentium? 4 processor, celeron? d processor bus interface unit e hub interface unit e pci express interface unit e ddr 2 memory interface unit t he mch incorporates an integrated pci express * interface. the pci express* interface allows the mch to directly interface with the pci express* devices . the mch also increases the main memory int erface bandwidth and maximum memory configuration with a 72 - bit wide memory interface. the mch integrates the following main functions: e an integrated high performance main memory subsystem e a pci express* bus which provides an interface to the pci - express devices ( fully compliant to the pci express* base specification, rev 1.0a ) e a dmi which provides an interface to the intel? ich7r free datasheet http://
functional architecture intel? server board S3000PT tps 10 revision 1.3 other features provided by the mch include the following: e full support of ecc on the ddr2 memory bus e twelve deep in - order queue , two deep defer queue e full support of un - buffered ddr2 ecc dimms e support for 256 - mb, 512 - mb, 1 - gb and 2 - gb ddr 2 memory modules 3.2.1.2 segment d pci - e xpress x8 in this board, the mch pcie lanes 0~7 are connected to an x8 pci - e riser connector directly through th e mch. it can support x1, x4, and x 8 pci - e add - in cards through a riser card . table 3 . segment e connections lane device lane 0~7 slot 1 (pci express* x8) 3.2.1.3 mch memory sub - system overview the mch supports a 72 - bit wide memory sub - s ystem that can support a maximum of 8 gb of ddr2 memory using 2 gb dimms. this configuration needs external registers for buffering the memory address and control signals. the four chip selects are registered inside the mch and need no external registers fo r chip selects. the memory interface runs at 533/667 mt/s. the memory interface supports a 72 - bit wide memory array. it uses seven teen address lines (ba [2:0] and ma [13:0]) and supports 256 - mb, 512 - mb , 1 - gb, and 2 - gb dram densities. the ddr dimm interface supports single - bit error correction, and multiple bit error detection . 3.2.1.3.1 ddr 2 configurations the ddr 2 interface supports up to 8 gb of main memory and supports single - and double - density dimms. the ddr 2 can be any industry - standard ddr 2 . the following tabl e shows the ddr 2 dimm technology supported. table 4 . supported ddr 2 module s ddr2 - 533/667 un - buffered sdram module matrix dimm capacity dimm organization sdram density sdram organization # sdram devices/rows/banks # address bits row s/banks/column 256mb 32m x 72 256mbit 32m x 8 9 /1 / 4 13 / 2 / 10 512mb 64m x 72 256mbit 32m x 8 18 / 2 / 4 13 / 2 / 10 512mb 64m x 72 512mbit 64m x 8 9 / 1 / 4 14 / 2 / 10 1gb 128m x 72 512mbit 64m x 8 18 / 2 / 4 14 / 2 / 10 1gb 128m x 72 1gbit 128m x 8 9 / 1 / 8 14 / 4 / 10 2gb 256m x 72 1gbit 128m x 8 18 / 2 / 8 14 / 8 / 10 free datasheet http://
intel? server board S3000PT tps functional architecture revision 1.3 11 3.2.2 i/o controller hub 3.2.2.1 intel? ich7r : i / o control ler hub 7r the intel? ich7r controller has several components. it provides the interface for a 32 - bit / 33 - mhz pci bus. the intel? ich7r controller can be both a master and a target on that pci bus and includes a usb 2.0 controller and an ide controller. the intel? ich7r controller is also responsible for much of the power management functions, with acpi control registers built in. i t also provides a number of gpio pins and has the lpc bus to support low - speed legacy i/o. the mch and intel? ich7r chips provide the pathway between the processor and the i/o systems. the mch is responsible for accepting access requests from the host (pro cessor) bus, and directing all i/o accesses to one of the pci buses or legacy i/o locations. if the cycle is directed to one of the pci express* segments, the mch communicates with the pci express* devices (add - in card, on board devices) through the pci ex press* interface. if the cycle is directed to the intel? ich7r controller , the cycle is output on the mchs dmi bus. all i/o for the board, including pci and pc - compatible i/o, is directed through the mch and then through the intel? ich7r provided pci bus e s . the intel? ich7 r controller is a multi - function device, housed in a 652 - pin m bga device. it provides the following: e a dmi bus e a pci 32 - bit/33 - mhz interface e an ide interface e an integrated s erial ata host controller e a usb controller e a pci express* x4 inte rface e two pci express* x 1 interface e a power management controller each function within the intel? ich7r controller has its own set of configuration registers. once configured, each appears to the system as a distinct hardware controller sharing the same pc i bus interface. the primary role of the intel? ich7 r controller is providing the gateway to all pc - compatible i/o devices and features. the board uses the following intel? ich7r features: e pci 32 - bit/33mhz interface to dedicated ati* es1000 video subsystem e lpc bus interface e x1 pci express* interface for intel? 82573e gigabit ethernet controller e x1 pci express* interface for intel? 82573 v gigabit ethernet controller e dmi (direct media interface) e integrated dual - port serial ata host controller e universal serial bus (usb) 2.0 interface e pc - compatible timer/counter and dma controllers e apic and 82 c 59 interrupt controller free datasheet http://
functional architecture intel? server board S3000PT tps 12 revision 1.3 e power management e system rtc e supports the smbus 2.0 specification e general - purpose i/o (gpio) the following are the descriptions of how each supporte d feature is used for the intel? ich7r controller on the board . 3.2.2.1.1 sata controller the intel? ich7r controller has an integrated sata host controller that supports independent dma operation on four ports and supports data transfer rates of up to 3.0 gb/s (300 mb/s). 3.2.2.2 compatibility modules (dma controller, timer/counters, interrupt controller) the dma controlle r incorporates the logic of two intel? 82c37 dma controllers, with seven independently programmable channels. channels 0 C 3 are hardwired to 8 - bit, count - by - byte transfers, and channels 5 C 7 are hardwired to 16 - bit, count - by - word transfers. any two of the seven dma channels can be programmed to support fast type - f transfers. the timer/counter block contains three counters that are equivalent in function to t hose found in one intel? 82c54 programmable interval timer. these three counters are combined to provide the system timer function, and speaker tone. the 14.31818 - mhz oscillator input provides the clock source for these three counters. the intel? ich7 r con troller provides an isa - compatible programmable interrupt controller ( pic) that incorporates the functionality of two, 82c59 interrupt controllers. the two interrupt controllers are cascaded so that 14 external and two internal interrupts are possible. in addition, the intel? ich7r controller supports a serial interrupt scheme. all of the register s in these modules can be read and restored. this is required to save and restore the system state after power has been removed and restored to the platform. 3.2.2.2.1 advan ced programmable interrupt controller (apic) in addition to the standard isa compatible programmable interrupt controller (pic) described in the previous section, the intel? ich7r incorporates the advanced programmable interrupt controller ( apic). 3.2.2.2.2 univers al serial bus (usb) controller the intel? ich7 r controller contains one ehci * usb 2.0 controller and four usb port s. the usb controller moves data between main memory and up to four usb connectors. all ports function identically and with the same bandwidth . the intel? server board S3000PT implemen ts four ports on the board. two external usb ports are provided on the back of the server board. the universal serial bus specification, revision 1.1, defines the external connectors. free datasheet http://
intel? server board S3000PT tps functional architecture revision 1.3 13 the third/ fourth usb port is optional and can be accessed by cabling from an internal 9 - pin connector located on the server board to an external usb port located either in front of or on the rear of a given chassis. 3.2.2.2.3 enhanced power management the intel? ich7 r controllers power managem ent functions include enhanced clock control and various low - power ( suspend) states (e.g., suspend - to - ram and suspend - to - disk). a hardware - based thermal management circuit permits a software - independent entrance to low - power states. the intel? ich7 r contro ller contains full support for the advanced configuration and power interface (acpi) specification, revision 3.0. the server board supports sleep states s1, s4, and s5. 3.3 memory sub - system the memory interface between the mch and the dimms is a 72 - bit (ecc) wide interface . there are two banks of dimms, labeled 1 and 2. bank 1 contains dimm socket locations dimm _1a and dimm _1b . bank 2 contains dimm socket locations dimm _2a and dimm _2b . the sockets associated with each bank , or channel, are located next to each other , and the dimm socket identifiers are marked on the base board silkscreen, near the dimm socket. when only two dimm modules are being used, the population order must be dimm_1a, dimm_1b to ensure dual - channel operating mode. in order to operate i n dual - channel dynamic paging mode, the following conditions must be met: e two identical dimms are installed, one each in dimm_1a and dimm_1b e four identical dimms are installed (one in each socket location) note : installing only three dimms is not supported . do not use dimms that are not matched ( same type and speed). use of identical memory parts is always the preferred method. see figure 3 for reference. the system design is free to populate or not to populate any rank on either channel, including either degenerate single channel case. free datasheet http://
functional architecture intel? server board S3000PT tps 14 revision 1.3 dimm and memory configurations must adhere to the following: e ddr2 533/667 , un - buffered , ddr 2 dimm modules e dimm organization: x72 ecc e pin count: 240 e dimm capacity:512 mb, 1 gb and 2 gb dimms e serial pd: jedec rev 2.0 e voltage options: 1.8 v e interface: sstl2 table 5 . memory bank labels and dimm population order location dimm label channel population order j 2d1 ( dimm_1a) a 1 j1d2 ( dimm_2a) a 3 j1d3 ( dimm_1b) b 2 j1d1 ( dimm_2 b ) b 4 figure 3 . memory bank label definition free datasheet http://
intel? server board S3000PT tps functional architecture revision 1.3 15 table 6 . characteristics of dual/single channel configuration with or without dynamic mode throughput level configuration charac teristics highest dual channel with dynamic paging mode all dimms matched dual channel without dynamic paging mode dimms matched from channel a to channel b dimms not matched within channels single channel with dynamic paging mode single dimm or dimms matched within a channel lowest single channel without dynamic paging mode dimms not matched 3.3.1 memory dimm support the board supports un - buffered (not registered) ddr 2 533/667 ecc dimms operating at 533/667 mt/s. only dimms tested and qualified by intel o r a designated memory test vendor are supported on this board . a list of qualified dimms is available at http://support.intel.com/support/motherboards/server/ . note : a ll dimms are suppo rted by design, but only fully qualified dimms will be supported on the board. the minimum supported dimm size is 256 mb. therefore, the minimum main memory configuration is 1 x 256 mb or 256 mb. the largest size dimm supported is 2 gb and as such, the max imum main memory configuration is 8 gb implemented by 4 x 2 - gb dimms. e only un - buffered ddr2 533/667 compliant, ecc x8 or x16 memory dimms are supported. e ecc single - bit errors (sbe) will be corrected; multiple - bit error (mbe) will only be detected. e intel? s erver board S3000PT supports intel? x4 single device data correction with x4 dimms. e the maximum mem ory capacity is 8 gb via four 2 - gb dimm modules. e the minimum memory capacity is 256 mb via a single 256 - mb dimm module. 3.4 i/o sub - system 3.4.1 pci subsystem there ar e three independent pci bus segments directed from the intel? ich7 r controller on the intel? server board S3000PT . pci segment a is a legacy pci bus while pci segments b and c are pci express*. free datasheet http://
functional architecture intel? server board S3000PT tps 16 revision 1.3 3.4.1.1.1 device ids (idsel) each device under the pci hub bridge has its idsel signal connected to one bit of ad (31:16), which acts as a chip select on the pci bus segment in configuration cycles. this determines a unique pci device id value for use in configuration cycles. the following table shows the bit to which each i dsel signal is attached for segment a devices and the corresponding device description. table 7 . segment a configuration ids idsel value device 20 ati* es1000 video controller 3.4.1.1.2 segment a arbitration pci segment a supports two pci devices: the intel? ich7 r and one pci bus master (nic). all pci masters must arbitrate for pci access, using resources supplied by the intel? ich7 r . the host bridge pci interface (ich7 r ) arbitration lines reqx* and gntx* are a special case in that they are internal to the host bridge. the following table defines the arbitration connections. table 8 . segment a arbitration connections server board signals device pci req_n 4 /gnt_n 4 ati* es1000 video controller 3.4.2 interrupt routing the bo ard interrupt architecture accommodates both pc - compatible pic mode and apic mode interrupts through use of the integrated i/o apics in the intel? ich7 r controller . 3.4.2.1 legacy interrupt routing for pc - compatible mode, the intel? ich7 r controller provides two 82c59 - compatible interrupt controllers. the two controllers are cascaded with interrupt levels 8 - 15 entering on level 2 of the primary interrupt controller (standard pc configuration). a single interrupt signal is presented to the processors, to which only one processor will respond for servicing. the intel? ich7r contains configuration registers that define which interrupt source logically maps to i/o apic intx pins. the intel? ich7 r controller handles both pci and irq interrupts. the intel? ich7r transla tes these to the apic bus. the numbers in the following table indicate the intel? ich7r pci interrupt input pin to which the associated device interrupt (inta, intb, intc, intd, int e , int f , int g , int h for pci bus and pxirq0 , pxirq1 , pxirq2 , pxirq3 for pci - x bus ) is connected. the intel? ich7r i/o apic exists on the i/o apic bus with the processors. free datasheet http://
intel? server board S3000PT tps functional architecture revision 1.3 17 table 9 . pci interrupt routing/sharing interrupt int a int b int c int d aties 1000 pirqc 3.4.2.2 apic interrupt routing for apic mode, the ser ver board interrupt architecture incorporates three intel ? i/o apic devices to manage and broadcast interrupts to local apics in each processor. the intel? i /o apics monitor ea ch interrupt on each pci device, including pci slots in addition to the isa comp atibility interrupts irq (0 - 15 ) . when an interrupt occurs, a message corresponding to the interrupt is sent across a three - wire serial interface to the local apics. the apic bus minimizes interrupt latency time for compatibility interrupt sources. the i/o apics can also supply greater than 16 interrupt levels to the processor(s). this apic bus consists of an apic clock and two bi - directional data lines. 3.4.2.3 legacy interrupt sources the following table recommends the logical interrupt mapping of interrupt sourc es on the board. the actual interrupt map is defined using configuration registers in the intel? ich7 r controller . table 10 . interrupt definitions isa interrupt description intr processor interrupt nmi nmi to processor irq0 syste m timer irq1 keyboard interrupt irq2 slave pic irq3 serial port 1 interrupt from super i/o* device, user - configurable irq4 serial port 1 interrupt from super i/o* device, user - configurable irq5 irq6 floppy disk irq7 generic irq8_l active low rtc i nterrupt irq9 sci* irq10 generic irq11 generic irq12 mouse interrupt irq13 f loating point processor irq14 compatibility ide interrupt from prim ary channel ide devices 0 and 1 irq15 secondary ide c able smi* syste m management interrupt. general - purpo se indicator sourced by the intel? ich7r c ontroller to the processors. free datasheet http://
functional architecture intel? server board S3000PT tps 18 revision 1.3 3.4.2.4 serialized irq support the intel? server board S3000PT supports a serialized interrupt delivery mechanism. serialized interrupt requests (serirq) consists of a start frame, a minimum o f 17 irq / data channels, and a stop frame. any slave device in the quiet mode may initiate the start frame. while in the continuous mode, the start frame is initiated by the host controller. 3.5 pci error handling the pci bus defines two error pins, perr# and serr#, for reporting pci parity errors and system errors, respectively. in the case of perr#, the pci bus master has the option to retry the offending transaction, or to report it using serr#. all other pci - related errors are reported by serr#. serr# is r outed to the nmi if enabled by the bios. free datasheet http://
intel? server board S3000PT tps functional architecture revision 1.3 19 figure 4 . interrupt routing diagram irq0 irq1 irq2 irq3 irq4 irq5 irq6 irq7 irq8 irq9 irq10 irq11 irq12 irq13 irq14 irq15 irq16 irq1 7 irq1 8 irq1 9 irq20 irq2 1 irq2 2 irq2 3 intel? ich7r controller ioapic 0 intel? ich7r controller mch intel? ich7r controller 8259pic cpu intr dmi interface free datasheet http://
functional architecture intel? server board S3000PT tps 20 revision 1.3 figure 5 . intel? ich7r controller interrupt routing diagram pirqb# pirqd# pirqc# pirqe# pirqf# pirqg# pirqh# pirqa# super i/o timer keyboard serial port2/isa serial port1/isa isa floppy/isa isa rtc sci/isa isa isa mouse/isa coprocessor error p_ide/isa not used cascade serialized irq interface serirq n/a n/a n/a serirq intel? ich7r controller interrupt routing pci interface n/a n/a ( supported by tumwater only) ati es1000 n/a n/a n/a free datasheet http://
intel? server board S3000PT tps functional architecture revision 1.3 21 3.5.1 video support the intel? server board s300 0pt includes an integrated stand alone ati * es1000 graphics engine tha t supports standard vga drivers with analog display capabilities. the graphics subsystem has 16 mb of dedicated memory to support the onboard video controller. the baseboard provides a standard 15 - pin vga connector at the rear of the system, in the i/o ope ning area. 3.5.1.1 video modes table 11 . video modes 2d video mode support 2d mode refresh rate (hz) 8 bpp 16 bpp 24 bpp 32 bpp 640x480 60, 72, 75, 90, 100 supported supported supported supported 800x600 60, 70, 75, 90, 100 supported supported supported supported 1024x768 60, 72, 75, 90, 100 supported supported supported supported 1280x1024 43, 60 supported supported supported supported 1280x1024 70, 72 supported C supported supported 3d video mode supp ort with z buffer enabled 3d mode refresh rate (hz) 8 bpp 16 bpp 24 bpp 32 bpp 640x480 60,72,75,90,100 supported supported supported supported 800x600 60,70,75,90,100 supported supported supported supported 1024x768 60,72,75,90,100 supported supported supported supported 128 0x1024 43,60,70,72 supported supported C C 3d video mode support with z buffer disabled 3d mode refresh rate (hz) 8 bpp 16 bpp 24 bpp 32 bpp 640x480 60,72,75,90,100 supported supported supported supported 800x600 60,70,75,90,100 supported supported supported supported 1024x768 60,72,75,90,100 supported supported supported supported 1280x1024 43,60,70,72 supported supported supported C 3.5.2 network interface controller (nic) the intel? server board S3000PT supports two 10/100 /1000 base - t network inter face s. e nic1 is an intel? 82573e gigabit ethernet controller resourced with a x1 pci express* interface from the intel? ich7r (pci segment c ) . e nic2 is an intel? 82 573v g igabit ethernet controller resourced with a x1 pci express* interface from the intel? i ch7r (pci segment b ) . e both the intel? 82573e and intel? 825 73v gigabit ethernet controllers are single, compact components with an integrated gigabit ethernet media access control (mac) and physical layer (phy) function. the intel? 82573e and intel? 82 573v gigabit ethernet controller allow for a gigabit ethernet implementation in a very small area that is footprint compatible with current generation 10/100 mbps fast ethernet designs. intel? 82573e /v integrate s fourth and fifth generation (respectively) giga bit mac design with fully integrated physical layer circuitry t o provide a standard ieee 802.3 ethernet free datasheet http://
functional architecture intel? server board S3000PT tps 22 revision 1.3 interface for 1000base - t, 100base - tx, and 10base - t applications (802.3, 802.3u, and 802.3ab). the controller is capable of transmitting and receiving da ta at rates of 1000 mbps, 100 mbps, or 10 mbps. 3.5.2.1 nic connector and status leds the nics drive two leds located on each network interface connector. table 12 . intel? 82573e interface connector ( nic1) led color led state condition off lan link is not established. on lan link is established. lef t green blinking lan activity is occurring. n/a off 10 mbit/sec data rate is selected. green on 100 mbit/sec data rate is selected. right yellow on 1000 mbit/sec data rate is selected. table 13 . intel? 82573 v interface connector ( nic2) led color led state condition off lan link is not established. on lan link is established. right green blinking lan activity is occurring. n/a off 10 mbit/sec data ra te is selected. green on 100 mbit/sec data rate is selected. left yellow on 1000 mbit/sec data rate is selected. 3.5.3 super i/o chip the smsc * sch5027 or sch5017 s io devices contain all of the necessary circuitry to control serial/parallel ports, floppy disk, ps/2 - compatible keyboard, mouse and hardware monitor controller. the baseboard implements the following features: e gpio s e one full functional serial port e one tx/rx only serial port for debug only e local hardware monitoring e wake up control e system health suppor t 3.5.3.1 serial ports the board provides a serial port implemented as an external 9 - pin serial port; an internal 3 - pin tx/rx only serial port is also provided. the following sections provide details on the use of the serial port . free datasheet http://
intel? server board S3000PT tps functional architecture revision 1.3 23 3.5.3.1.1 serial port a serial a is a stan dard db9 interface located at the rear i/o panel of the server board, above the video connector. serial a is designated by a serial_ a on the silkscreen. the reference designator is j3a1. serial b is a 3 - pin header interface located near the sio . serial b i s designated by a serial_ b on the silkscreen. the reference designator is j2b1 . table 14 . serial a header pin - out pin signal name serial port a header pin - out 1 dcd 2 rx d 3 tx d 4 dtr 5 gnd 6 dsr 7 rts 8 cts 9 ri table 15 . serial b header pin - out pin signal name serial port b header pin - out 1 rx d 2 gnd 3 tx d gnd 3 - pin serial b header tx rx 1 2 3 3.5.3.2 keyboard and mouse support usb ports can be used to support keyboard and mouse. no ps / 2 port is available. 3.5.3.3 wake - up control the super i/o contains functionality that allows various events to control the power - on and power - off the system. 3.5.4 bios flash the board incorporates a spi flash memory which can work with 16 megabit spi ser ial flash devices that provide 1024k x 8 or 512 k x 8 of bios and non - volatile storage space. the flash device is connected through th e spi bus from the intel? ich7r controller . free datasheet http://
functional architecture intel? server board S3000PT tps 24 revision 1.3 3.5.5 system health support smbus 2.0 is the interface used to connect the system he alth sensors of the super i/o smsc* sch5027 or sch5017 chip. the following is supported: e three pwm - based fan controls and six fan speed tachometers e software or local temperature feedback control e voltage measurement and monitor 3.6 replacing the back - up battery the lithium battery on the server board powers the rtc for up to ten years in the absence of power. when the battery starts to weaken, it loses voltage, and the server settings stored in cmos ram in the rtc (for example, the date and time) may be wrong. c ontact your customer service representative or dealer for a list of approved devices. warning danger of explosion if battery is incorrectly replaced. replace only with the same or equivalent type recommended by the equipment manufacturer. discard used ba tteries according to manufacturers instructions. advarsel ! lithiumbatteri - eksplosionsfare ved fejlagtig h?ndtering. udskiftning m? kun ske med batteri af samme fabrikat og type. levr det brugte batteri tilbage til leverand?ren. advarsel lithiumbatt eri - eksplosjonsfare. ved utskifting benyttes kun batteri som anbefalt av apparatfabrikanten. brukt batteri returneres apparatleverand?ren. varning explosionsfara vid felaktigt batteribyte. anv?nd samma batterityp eller en ekvivalent typ som rekommender as av apparattillverkaren. kassera anv?nt batteri enligt fabrikantens instruktion. varoitus paristo voi r?j?ht??, jos se on virheellisesti asennettu. vaihda paristo ainoastaan laitevalmistajan suosittelemaan tyyppiin. h?vit? k?ytetty paristo valmistajan ohjeiden mukaisesti. free datasheet http://
intel? server board S3000PT system bios revision 1.3 25 4. system bios 4.1 bios identification string the bios identification string is used to uniquely identify the revision of the bios being used on the server. the string is formatted as follows: boardfamilyid.oemid.majorrev.minorrev.buildid.b uilddatetime where: e boardfamilyid = string name for this board family. e oemid = three - character oem id. 86b is used for intel epsd. e majorrev = two decimal digits e minorrev = two decimal digits e buildid = four decimal digits e builddatetime = build date and t ime in mmddyyyyhhmm format: - mm = two - digit month - dd = two - digit day of month - yyyy = four - digit year - hh = two - digit hour using 24 hour clock - mm = two - digit minute 4.2 logo / diagnostic window the logo / diagnostic window may be i n one of two forms. in quiet b o ot mode, a logo splash screen is displayed . in v erbose mode, a system summary and diagnostic screen is displayed. the default is to display the logo in q uiet b oot mode. if no logo is present in the flash rom, or if q uiet b oot mode is disabled in the system configuration, the summary and diagnostic screen is displayed. the diagnostic screen consists of the following information : e bios id. e total memory detected (t otal size of all installed dimms) e processor information (intel branded string, speed, and number of physical processors identified) e types of keyboards detected , if plugged in e types of mouse devices detected , if plugged in free datasheet http://
system bios intel? server board S3000PT tps 26 revision 1.3 4.3 bios setup utility the bios setup utility is a text - based utility that allows the user to configure the system and view current settings and environment information for the platform devices. the setup utility controls the platform's built - in devices. the bios setup interface consists of a number of pages or screens. each page contains information or links to other pages. the first page in setup displays a list of general categories as links. these links lead to pages containing a specific categorys configuration. the following sections describe the look and behavior for the platform setup. 4.3.1 operation bios setup has the following f eatures: e localization. the intel server board bios will only be available in english. e bios setup is functional via console redirection over various terminal emulation standards. this may limit some functionality for compatibility , e.g. , usage of colors or some keys or key sequences or support of pointing devices. 4.3.1.1 setup page layout the setup page layout is sectioned into functional areas. each occupies a specific area of the screen and has dedicated functionality. the following table lists and describes eac h functional area. table 16 . bios setup page layout functional area description title bar the title bar is located at the top of the screen and displays the title of the form ( page) the user is currently viewing. it may also displa y navigational information. setup item list the setup item list is a set of controllable and informational items. each item in the list occupies the left and center columns in the middle of the screen. the left column, the "setup item", is the subject of the item. the middle column, the "option", contains an informational value or choices of the subject. a setup item may also be a hyperlink that is used to navigate formsets (pages). when it is a hyperlink, a setup item only occupies the setup item colum n. item specific help area the item specific help area is located on the right side of the screen and contains help text for the highlighted setup item. help information includes the meaning and usage of the item, allowable values, effects of the options, etc. keyboard command bar the keyboard command bar is located at the bottom right of the screen and continuously displays help for keyboard special keys and navigation keys. the keyboard command bar is context - sensitive it displays keys relevant to curre nt page and mode. status bar the status bar occupies the bottom line of the screen. this line would display the bios id . free datasheet http://
intel? server board S3000PT system bios revision 1.3 27 4.3.1.2 entering bios setup bios setup is started by pressing during boot time when the oem or intel logo is displayed. when quiet bo ot is disabled, there will be a message press to enter setup displayed on the diagnostics screen. 4.3.1.3 keyboard commands the bottom right portion of the setup screen provides a list of commands that are used to navigate through the setup utility. these c ommands are displayed at all times. each setup menu page contains a number of features. except those used for informative purposes, each feature is associated with a value field. this field contains user - selectable parameters. depending on the security opt ion chosen and in effect by the password, a menu features value may or may not be changeable. if a value is non - changeable, the features value field is inaccessible. it displays as grayed out. the keyboard command bar supports the following: table 17 . bios setup: keyboard command bar key option description execute command the key is used to activate sub - menus when the selected feature is a sub - menu, or to display a pick list if a selected option has a value field , or to select a sub - field for multi - valued features like time and date. if a pick list is displayed, the key will select the currently highlighted item, undo the pick list, and return the focus to the parent menu. exit the key provide s a mechanism for backing out of any field. this key will undo the pressing of the enter key. when the key is pressed while editing any field or selecting features of a menu, the parent menu is re - entered. when the key is pressed in any sub - me nu, the parent menu is re - entered. when the key is pressed in any major menu, the exit confirmation window is displayed and the user is asked whether changes can be discarded. if no is selected and the key is pressed, or if the key is pressed, the user is returned to where he/she was before was pressed, without affecting any existing any settings. if yes is selected and the key is pressed, setup is exited and the bios returns to the main system options menu screen. e- s elect item the up arrow is used to select the previous value in a pick list, or the previous option in a menu item's option list. the selected item must then be activated by pressing the key. e select item the down arrow is used to select the next value in a menu items option list, or a value fields pick list. the selected item must then be activated by pressing the key. e? select menu the left and right arrow keys are used to move between the major menu pages. the keys have no affect if a sub - menu or pick list is displayed. select field the key is used to move between fields. for example, can be used to move from hours to minutes in the time item in the main menu. - change value the minus key on the keypad is used to c hange the value of the current item to the previous value. this key scrolls through the values in the associated pick list without displaying the full list. free datasheet http://
system bios intel? server board S3000PT tps 28 revision 1.3 key option description + change value the plus key on the keypad is used to change the value of the current menu item to the next value. this key scrolls through the values in the associated pick list without displaying the full list. on 106 - key japanese keyboards, the plus key has a different scan code than the plus key on the other keyboard, but will have the same effect. setup defaults pressing causes the following to appear: load optimized defaults? (y/n) if the key is pressed, all setup fields are set to their default values. if the key is pressed, or if the key is pressed, the user is retur ned to where they were before was pressed without affecting any existing field values save and exit pressing causes the following message to appear: save configuration and reset? (y/n) if the key is pressed, all changes are saved a nd setup is exited. if the key is pressed, or the key is pressed, the user is returned to where they were before was pressed without affecting any existing values. 4.3.1.4 menu selection bar the menu selection bar is located at the top of the scr een. it displays the major menu selections available to the user. 4.3.2 server platform setup screens the following sections describe the screens available for the configuration of a server platform. in these sections, tables are used to describe the contents of each screen. these tables follow the following guidelines: e the text and values in the setup item, options, and help columns in the tables are displayed on the bios setup screens. e bold text in the options column of the tables indicates default values. the se values are not displayed in bold on the setup screen. the bold text in this document is to serve as a reference point. e the comments column provides additional information where it may be helpful. this information does not appear in the bios setup screen s. e information in the screen shots that is enclosed in brackets (< >) indicates text that varies, depending on the option(s) installed. for example is replaced by the actual current date. e information that is enclosed in square brackets ([ ]) in the tables indicates areas where the user needs to type in text instead of selecting from a provided option. free datasheet http://
intel? server board S3000PT system bios revision 1.3 29 4.3.2.1 main screen the main screen is the screen that is first displayed when bios setup is entered. e main advanced security server management boo t options boot manager error manager exit e e logged in as e e e bios version e e e s3000.86b.yy.xx.zzzz e e e e e e bios build date e e e e e e e e e quiet boot enable /disable e e e post error pause enable /disable e e e e e e system date < current date> e e e system time e e e e e figure 6 . setup utility main screen display table 18 . setup utility main screen fields setup item options help text comment bios version no en try allowed information only. displays the current bios version. yy = major version xx = minor version zzzz = build number bios build date no entry allowed information only. displays the current bios build date. quiet boot enable disable if enabled, b ios splash screen is displayed. if disabled, bios post messages are displayed. post error pause enable disable if enabled, the system will wait for user intervention on critical post errors. if disabled, the system will boot with no intervention, if poss ible. the post pause will take the system to the error manager to review the errors. free datasheet http://
system bios intel? server board S3000PT tps 30 revision 1.3 setup item options help text comment system date [mm/dd/yyyy] month valid values are 1 to 12. day valid values are 1 to 31. year valid values are 1998 to 2099. help text depends on the sub - field selected (mo nth, day, or year). system time [hh:mm:ss] hours valid values are 0 to 23. minutes valid values are 0 to 59. seconds valid values are 0 to 59. help text depends on the sub - field selected (hours, minutes, seconds). 4.3.2.2 advanced screen the advanced screen pro vides an access point to choose to configure several options. on this screen, the user selects the option that is to be configured. configurations are performed on the selected screen, not directly on the advanced screen. to access this screen from the mai n screen, select advanced. main advanced security server management boot options boot manager error manager exit e e e ? processor e e ? memory e e ? ide controller e e ? serial port e e ? usb controller e e ? pci e e ? power e e ? boot configurati on e e e e ? hardware health configuration e e figure 7 . setup utility advanced screen display free datasheet http://
intel? server board S3000PT system bios revision 1.3 31 4.3.2.2.1 processor screen the processor screen provides a place for the user to view the processor core frequency, system bus frequency, an d enable or disable several processor options. the user can also select an option to view information about a specific processor. to access this screen from the main screen, select advanced | processor. advanced processor processor fami ly core frequency system bus frequency boot processor number l2 cache ram cpuid regist er intel (r) em64t < > hyperthreading technology enabled / disabled enhanced speed s tep enabled / disabled execute disable bit enabled / disabled virtualization technology enabled/ disabled figure 8 . setup utility processor configuration screen display table 19 . setup utility processor configuration screen fields setup item options help text comment processor family no entry allowed in formation only. core frequency no entry allowed frequency at which processors currently run. information only. system bus frequency no entry allowed current frequency of the processor front side bus. information only. boot processor number no entry allo wed information only. l2 cache ram no entry allowed information only. cpuid register no entry allowed information only. intel (r) em64t no entry allowed information only. free datasheet http://
system bios intel? server board S3000PT tps 32 revision 1 .3 setup item options help text comment hyperthreading technology enable disable enables or disables intel? hyper - thr eading technology on the processors. select disabled if your operation s ystem is microsoft windows 2000 * . enhanced speed s tep enable disable enhanced intel ? speeds tep technology. select enable to allow the os to reduce power consum p tion. virtualization technology enable disable when enabled, a virtual machine monitor can utilize the additional hardware capabilities provided by intel ? virtualization technology displayed only when the processor has the vt function. execute disable bit enable disable exec ute disable bit featu re (xd bit). select enabled to p revent data pages from being used by malicious software to execute code. 4.3.2.2.2 memory screen the memory screen provides a place for the user to view details about the system memory dimms that are installed. on this screen, the user can select an option to open the configure memory ras and performance screen. to access this screen from the main screen, select advanced | memory. advanced memory total memory current memory configuration < single channel/dual channel > memory channel a slot not installed / size info memory channel a slot not installed / size info memory channel b slot not installed / size info memory channel b slot not in stalled / size info memory correction ecc /non - ecc figure 9 . setup utility memory configuration screen display free datasheet http://
intel? server board S3000PT system bios revision 1.3 33 table 20 . setup utility memory configuration screen fields setup item optio ns help text comment total memory no entry allowed information only. the amount of memory available in the system in the form of installed dimms, in units of mb or gb. current configuration no entry allowed information only. displays one of the followi ng: single channel dual channel dimm # no entry allowed displays the state of each dimm slot present on the board. each dimm slot field reflects one of the following possible states: size info : there is a dimm installed i n this slot and the size informa tion is displayed not install ed: there is no dimm installed i n this slot. memor y correction ecc non - ecc ecc non - ecc 4.3.2.2.3 sata controller screen the sata controller screen provides fields to configure sata hard disk drives. it also provides information on th e hard disk drives that are installed. advanced ide controller onboard pata controller enabled / disable onboard sata controller enabled / disable sata mode enhanced / legacy ahci mode enabled / disabled configure sata as raid enable d / disabled ? primary ide master not installed/ ? primary ide slave not installed/ ? sata port 0 not installed/ ? sata port 1 not installed/ ? sata port 2 not installed/ ? sata port 3 not installed/ figure 10 . setup utility sata controller configuration screen display free datasheet http://
system bios intel? server board S3000PT tps 34 revision 1.3 table 21 . setup utility ata controller configuration screen fields setup item opt ion help text comment onboard sata controller enable / disable help: onboard sata controller when enabled, the sata cont r oller can be configured in ide, raid, or ahci mode. raid and ahci modes are mutually exclusive. sata mode enhanced / legacy help: sa ta mode in legacy mode, bios can enumerate only four drives. it provides four options to choose a mix of sata and pata drives. if sata only is chosen, four sata drives can be enumerated. if pata only is chosen, only two ide drives will be enumerated. if pata primary, sata secondary is chosen, pata will be the primary channel and sata ports 1 and 3 will emulate secondary ata channel master/slave. if sata primary, pata secondary is chosen, sata ports 0, 2 and both ide ports will be enumerated. in enhanced mode, the bios is not limited to legacy pata four - drive limitations, and can enumerate the two pata drives and four sata drives (totaling six drives) regardless of ahci mode, and can list/boot to the remaining two sata drives as well with ahci sup port. ahci and raid modes are supported onl y when sata mode is selected as enhanced. ahci mode enable / disable help: ahci mode unavailable if the sata mode is legacy or if raid mode is selected. if ahci is enabled, no information for hdd will be dis played because the bios does not identify any drives when ahci is enabled. the identification and configuration is left to the ahci option rom. a user will not see any hdd information in bios setup. free datasheet http://
intel? server board S3000PT system bios revision 1.3 35 configure sata as raid enable / disable help: configure sata as raid unavailable when ahci mode is enabled. this mode can be selected only when the sata cont r oller is in enhanced mode. staggard spin up support enable / disable help: staggard spin up support available only when ahci mode is enabled sata port 0 disabled / drive information information only; unavailable when ahci or raid mode is enabled sata port 1 disabled / drive information information only; this field is unavailable when ahci or raid mode is enabled 4.3.2.2.4 serial ports screen the serial ports screen provides fields to configure the serial a [com 1]. to access this screen from the main screen, select advanced | serial port. e advanced e serial port com1 enable enable /disable address 3f8h / 2f8h / 3e8h / 2e8h irq 3 or 4 e e figure 11 . setup utility serial port configuration screen display table 22 . setup utility serial ports configuration screen fields setup item option help text comment com1 enable enabled disabled e nables or disables com1 port. address 3f8h / 2f8h / 3e8h / 2e8h selects the base i/o address for com1. irq 3 / 4 selects the interrupt request line for com1. free datasheet http://
system bios intel? server board S3000PT tps 36 revision 1.3 4.3.2.2.5 usb controller screen advanced usb function module version 08.04.02 usb devices enabled: usb controller enabled / disabled legacy usb support enabled / disabled / auto port 60/64 emulation enabled / disabled usb mass storage device enabled / disabled / auto usb 2.0 controller enabled / disabled usb mass storage emulation generic usb flash drive auto / floppy / forced fdd / hard disk / cd - rom figure 12 . setup utility usb controller configuration screen display table 23 . setup utility usb controller configuration screen fields setup item option help text comment module version usb driver version information only usb devices enabled: shows number of usb devices in syste m information only usb controller enabled disabled if disabled, all of the usb controllers will be turned off and inaccessable by the os. legacy usb support enabled disabled auto enables legacy usb support. auto option disables legacy support if no usb devices are connected. port 60/64 emulation enabled / disabled enables i/o port 60h/64h emulation support. this should be enabled for the complete usb keyboard legac y support for non - usb aware operating systems . usb 2.0 controller enabled disabled if d isabled, all of the usb 2.0 controller will be turned off and inaccessable by the os. free datasheet http://
intel? server board S3000PT system bios revision 1.3 37 generic usb flash drive auto floppy forced fdd hard disk cd - rom if auto, the usb device less than 530mb will be enumerated as floppy. forced fdd option can be used to f orce hdd formatted drive to boot as fdd (e.g. , zip drive) 4.3.2.2.6 pci screen the pci screen provides fields to configure pci add - in cards, the onboard nic controllers, and video options. to access this screen from the main screen, select advanced | pci . e e a dvanced e pci onboard nic 1 enabled / disabled onboard nic2 enabled / disabled figure 13 . setup utility pci configuration screen display table 24 . setup utility pci configuration sc reen fields setup item option help text comment onboard nic 1 enabled disabled enables or disables the primary network controller . onboard nic 2 enabled disabled enables or disables the secondary network controller . 4.3.2.2.7 power the system power configurati on page provides fields to configure the power state after certain events . to access this screen from the main screen, select advanced | power. free datasheet http://
system bios intel? server board S3000PT tps 38 revision 1.3 e advanced e power after power failure power off / last state/ power on wake on lan from s5 power off / power on figure 14 . setup utility power screen display setup item option help text comment after power failure power off last state power on determin e s the mode of operation if a power loss occurs. sta ys off: s ystem will remain off once power is restored. last state: res t ores system to th e same state it was before power failed. wake on lan from s5 power off power on determines the action taken when the system power is off and a pci power managemen t wake - up event occurs. table 25 . setup utility power screen fields boot configuration the boot configuration screen provides information on the boot devices . to access this screen from the main screen, select advanced | boot co nfiguration . e advanced e boot configuration numlock on / off figure 15 . setup utility boot configuration screen display free datasheet http://
intel? server board S3000PT system bi os revision 1.3 39 table 26 . setup utility system acoustic and performance co nfiguration screen fields setup item option help text comment numlock on off turns keyboard numlo ck on or off . system boot with numlock default setting to on or off. 4.3.2.2.8 hardware health configuration the hardware health configuration screen provides for con figuration and display of the hardware monitor. to access this screen from the main screen, select advanced | hardware health configuration . e advanced e ? hardware monitor auto fan control enabled / disabled figure 16 . setup utility hardware health configuration screen display setup item option help text comment hardware monitor view the hardware monitor information. auto fan control enabled / disabled enable / disable auto fan control. if enabled, fan speed will be adjusted automatically according to the temperature; if disabled, all fans will run at full speed. free datasheet http://
system bios intel? server board S3000PT tps 40 revision 1.3 4.3.2.3 hardware monitor screen e advanced hardware monitor cpu temperature system temperature dimm temperature fan1 speed fa n2 speed fan3 speed fan4 speed fan5 speed fan6 speed +1.5v +vccp vcc +5v +12v vtr vbat figure 17 . setup utility hardware monitor screen display 4.3.2.4 security screen the security screen provides fields to enable and set the user and administrative password s. to access this screen from the main screen, select the security option. free datasheet http://
intel? server board S3000PT system bios revision 1.3 41 e main advanced security server management boot options boot manager error manager exit admin password installed /not installed user password installed/not installed admin password user password figure 18 . setup utility security configuration screen display table 27 . setup utility security config uration screen fields setup item option help text comment admin password installed not installed indicates the status of the administrator password. information only. disabled if the password is blank. user password installed not installed indicates th e status of the user password. information only, disabled if the password is blank. admin password sets administrative password with maximum length of 7 characters. this option is only to control access to setup. administrator has full access to all setu p items. clearing the admin password will also clear the user password. the way to clear the admin password is to press the enter key and confirm again. user password sets user password with manimum length of 7 characters. available only if the adminis trator password is installed. this option only protects setup. user password only has limited acces to setup items. 4.3.2.5 server management screen the server management screen provides fields to configure several server management features. it also provides an access point to the screens for configuring console redirection and displaying system information. to access this screen from the main screen, select the server management option. free datasheet http://
system bios intel? server board S3000PT tps 42 revision 1.3 e main advanced security server management boot options boot manager exi t e clear system event log enabled / disabled event logging enabled / disabled ecc event logging enabled / disabled event log area status available / full o/s boot wd timer enabled / disabled asf support enabled / disabled e nter amtbx setup enabled / disabled reset intel? amt defaults boot to network enabled / disabled ? view event log ? console redirection ? system information figure 19 . setup utility server management configuration screen display table 28 . setup utility server management configurati on screen fields setup item option help text comment clear system event log enabled / disabled clear system event log. will reset to disabled after reboot . event logging enabled / disabled enabled / disabled event logging ecc event logging enabled / disabled enabled / disabled ecc event logging event log area status information only o/s boot wd timer enabled / disabled o/s boot watchdog timer pxe o/s boot timeout enabled / disabled pxe o/s boot timeout asf support enabled / disabled enable a sf support or not free datasheet http://
intel? server board S3000PT system bios revision 1.3 43 setup item option help text comment enter amtbx setup enabled / disabled enable or disable int el? amt (active management techno logy) reset intel ? amt defaults this allows user to reset intel ? amt to its default state. this item only shows up when asf support is enabl ed. selecting this item will reset the intel ? amt password. boot to network enabled / disabled enable or disable boot to network ( pxe) view event log view the events. see section 4.3.2.5.1 . console redirection console red irection see section 4.3.2.5.2 . system information system information see section 4.3.2.5.3 . 4.3.2.5.1 view event log the view event log screen displays all th e events that were logged in the event log . t he time of occurrence field displays the last time a specific event occurred . e server management e views the events event type (count) time of occurrence chassis intrusion (01) 4.3.2.5.2 console redirection screen the console redi rection screen provides a way to enable or disable console redirection and to configure the connection options for this feature. to access this screen from the main screen, selec t server management | console redirection . free datasheet http://
system bios intel? server boa rd S3000PT tps 44 revision 1.3 e server management e console redirection console redirection disabled / enabled flow control none - rts/cts - baud rate 9.6k / 19.2k / 38.4k / 57.6k / 115.2k terminal type pc - ansi / vt100 / vt100+ / vt - utf8 figure 20 . setup utility console redirection screen display table 29 . setup utility console redirection configuration fields setup item option help text comment console redirection disabled enabled enables and disables the ability of the system to redi rect screen data across a serial connection . flow control none rts/cts sets the handshake protocol the bios should expect from the remote console redirection application . baud rate 9 . 6 k 19.2k 36.4k 57.6k 115.2k sets the communication speed for the red irection data . terminal type vt100 vt100+ vt - utf8 pc - ansi sets the character formatting for the console redirection screen . free datasheet http://
intel? server board S3000PT system bios revision 1.3 45 4.3.2.5.3 server mangement system information screen the server management system informatio n screen displays part numbers, serial numbers , and firmware revisions. to access this screen from the main screen, selec t server management | system information. e server management e system information board part number board serial number system part number system seria l number chassis part number chassis serial number uuid figure 21 . setup utility server management system information screen display table 30 . setup utility server management syste m information fields setup item option help text comment board part number information only board serial number information only system part number information only system serial number information only chas s is part number information only chas s is serial number information only uuid information only free datasheet http://
system bios intel? server board S3000PT tps 46 revision 1.3 4.3.2.6 boot options the boot options screen displays all the boot devices an d provides the user with the ability to set the order of boot options. e main advanced security server management bo ot options boot manager error manager exit e boot timeout 10 / any figure boot options # n efi shell / list of the boot devices figure 22 . setup utility boot options display table 31 . setup utility error manager screen fields setup item option help text comment boot tmeout 10 set the def a ult timeout before system boot. a value of 65535 will disable the timeout completely. boot option #n efi shell / list of boot devices set the sys tem boot order . 4.3.2.7 boot manager the boot manager screen displays all the boot devices an d provides the user with the ability to b oot the system directly from the selected item without restarting the system . e main advanced security server management boo t options boot manager error manager exit e a list of boot devices figure 23 . setup utility boot options display free datasheet http://
intel? server board S3000PT system bios revision 1.3 47 table 32 . setup utility error manager screen fields setup item option hel p text comment a list of boot devices # boot system using the selected item . can boot the system from the selected item by pressing enter . 4.3.2.8 error manager screen the error manager screen displays any errors encountered during post. error manager e xit list of errors that have occurred in the system. figure 24 . setup utility error manager screen display table 33 . setup utility error manager screen fields setup item option help text comment displays system errors 4.3.2.9 exit screen the exit screen allows the user to choose to save or discard the configuration changes made on the other screens. it also provides a method to restore the server to factory defaults or t o save or restore a set of user - defined default values. if restore defaults is selected, the default settings, noted in bold in the tables in this section , will be applied. if restore user default values is selected, the system is restored to the default values that the user saved earlier, instead of being restored to the factory defaults. free datasheet http://
system bios intel? server board S3000PT tps 48 revision 1.3 e main advanced security server management boot options boot manager error manager exit e save changes and exit discard changes and exit save changes discard changes restore defaults save as user default values restore user default values figure 25 . setup utility exit screen display table 34 . setup utility exit screen fields setup item option help text comment save changes and exit apply current setup values and exit bios setup. user is prompted for confirmation only if any of the setup fields were modified. discard changes and exit ignore changes made to values and exit bios setup . user is prompted for confirmation only if any of the setup fields were modified. save changes apply current values and continue bios setup. user is prompted for confirmation only if any of the setup fields were modified. discard changes undo changes made to values and continue bios setup. user is prompted for confirmation only if any of the setup fields were modified. restore defaults restore default bios setup values. user is prompted for confirmation. the bios will load the defaults on the next re boot. save user default values save current values so they can be restored later. restore user default values restore previously saved user default s . user is prompted for confirmation. free datasheet http://
intel? server board S3000PT system bios revision 1.3 49 4.4 loading bios defaults different mechanisms exist for resetting t he system configuration to the default values. when a request to reset the system configuration is detected, the bios loads the default system configuration values during the next post. the request to reset the system to the defaults can be sent in the fol lowing ways: e a request to reset the system configuration can be generated using the bios system configuration utility (setup). e a reset system configuration request can be generated by moving the clear system configuration jumper. free datasheet http://
platform management architecture intel? server board S3000PT tps 50 revision 1.3 5. platform managem ent architecture the bios supports many standards - based server management features and several proprietary features. 5.1 console redirection the bios supports redirection of both video and keyboard via a serial link (com port). when console redirection is ena bled, the local (host server) keyboard input and post video output are passed both to the local keyboard and video connections, and to the remote console through the serial link. keyboard inputs from both sources are considered valid and video is displayed to both outputs. as an option, the system can be operated without a host keyboard or monitor attached to the system and can run entirely via the remote console, including bios setup. 5.1.1 serial configuration settings both emp and console redirection require n, 8, 1 mode (no parity, 8 - bit data, 1 stop bit). the bios does not require that the splash logo be turned off for console redirection to function. the bios supports multiple consoles, some of which are in graphics mode and some in text mode. the graphics consoles can display the logo and the text consoles can receive the redirected text. console redirection ends at the beginning of the legacy operating system boot (int 19h). the operating system is responsible for continuing the redirection from that point . 5.1.2 keystroke mappings during console redirection, the remote terminal sends keystrokes to the local server. the remote terminal may be a dumb terminal with a direct connection running a communication program. the keystroke mappings follow vt - utf8 format wit h the following extensions. 5.1.2.1 setup alias keys the and - function key combinations are synonyms for the or setup key. they are implemented and documented, but are not to be prompted for in screen messages. these hot keys are defined for co nsole redirection support, and are not to be implemented for locally attached keyboards. 5.1.2.2 standalone key for headless operation the microsoft headless design guidelines describes a specific implementation for the key as a single standalone keyst roke: e followed by a two - second pause must be interpreted as a single escape. e followed within two seconds by one or more characters that do not form a sequence described in this specification must be interpreted as plus the character or c haracters, not as an escape sequence. free datasheet http://
intel ? server board S3000PT platform management architecture revision 1.3 51 the escape sequence in the following table is an input sequence. this means it is sent to the bios from the remote terminal. table 35 . console redirection escape sequences for headless operatio n escape sequence description rrr this will be implement ed but will default to disabled. remote console reset 5.1.3 limitations e bios c onsole redirection terminates after an efi - aware operating system calls efi exit boot services. the opera ting system is responsible for continuing console redirection after that. e bios console redirection is a text console. graphical data, such as a logo, is not redirected. 5.2 intel ? active management technology (amt) intel ? active management technology architec ture is based on market demand for a platform management solution that provides remote management capabilities independent of system power states. the intel? amt architecture is centered around the intel? ich7r io controller and intel? 82573 gigabit lan co mponents. the intel? ich7r controller provides an interface to a new spi flash device for potential cost savings. because intel? amt depends on the availability of the intel? 82573 pci manageability functions, the intel? amt does not operate with third - pa rty lans. the main ob jectives of intel ? amt are: e deployable C intel? amt uses existing protocols and services available in todays it networks to minimize cost. intel? amt is constrained to the use of dhcp, dns, soap/xml/http, and tls; which are available on most it networks today. e highly available C the ability to provide remote management in the event of operating system or hardware failure. intel? amt provides baseline services whenever there is (at the minimum) auxiliary power available to the platform. currently, system auxiliary power is maintained by the main power supply when the system is plugged into the wall. this will significantly reduce it expenses for system repair. e os - i ndependent agent C baseline platform management capabilities that simplify system management running different operating system types and versions. intel? amt provides common remote management and persistent storage features that run independently of the operating system. e secure and tamper resistant - intel? amt provides access control, data security, and protection against attacks by using standard security protocols (e.g., tls) and application - level security mechanisms. intel? amt also provides tamper resistance to prevent the end - user from removing or disabling remote manageme nt service. free datasheet http://
platform management architecture intel? server board S3000PT tps 52 revision 1.3 the intel? 82573 controller is a multi - functional device with an embedded microcontroller for manageability purposes. manageability functions of the intel? 82573 pci are as follows: e ide - r C for remote boot and software installation e serial port C for k eyboard and text redirection e kcs C for configuration of the manageability content the intel? 82573e controller is a pci express* gbit ethernet endpoint device, the first gbe controller to support intel? amt as the next - generation client manageabil ity architecture. the intel? 82573e controller provides three pci functions for management purposes: serial port, ide, and kcs. when the intel? amt is disabled, the intel? 82573e controller disables these three pci functions. when these management function s are disable d, the functions do not respond to pci configuration cycles (effectively becoming invisible to software). when intel? amt is enabled , the intel? 82573e controller enables the pci functions, which appear to software as standard pci devices. ser ial port function: the serial port function supports redirection of keyboard and post messages to a terminal window on a remote console. the keyboard and text redirection enables the control of the client machine through the network without the need to be physically near that machine. text and keyboard redirection allows the remote machine to monitor post progress of the client machine and allows the remote machine to control and configure the client by entering bios setup. the intel? 82573e controller redi rects data from the serial port to the management console via the lan; hence, providing serial over lan (sol) capability. ide function: the ide function provides ide - r, an ide redirection interface that provides client connection to management console ata/ atapi devices. when booting from ide - r, the ide - r interface will send the clients ata/atapi command to the management console. the management console responds back to the client. a remote machine can setup diagnostic software or an operating system instal lation image and direct the client to boot from ide - r. the ide - r interface is the same as the ide interface and is compliant with ata/atapi - 6 specifications. ide - r does not conflict with the usage of pxe boot. the system can support both interfaces and ca n continue to boot from pxe as with any other boot devices. however, during a management boot session, the intel? amt solution will use ide - r when remote boot is required. the devices attached to the ide - r channel are only visible to software during a mana gement boot session. during a normal boot session, the ide - r channel appears as no device present. kcs function: the kcs (keyboard controller style) function provides a physical interface used to convey messages between the host software and the amt device . the kcs function defines a set of memory - mapped io (mmio) registers. these mmio registers follow the usage model used in the intel? 8742 universal peripheral interface microcontroller. the term keyboard controller style reflects the fact that the intel ? 8742 interface is used as the system keyboard controller interface in pc architecture computer systems. the amt bios extension (amtx) is provided by intel and is included in the system bios at build time. the amtx module communicates with the intel? 8257 3e firmware via the kcs interface. the amtx module collects system hardware configuration via acpi and the smbios tables, and sends hardware information to the remote management system via the kcs interface. free datasheet http://
intel? server board S3000PT platform management architecture revision 1.3 53 table 36 . function lis t function vendor id device id intel? 82573e lan 0x8086 0x108b/0x108c (v/e) ide 0x8086 0x108d serial port 0x8086 0x108f kcs 0x8086 0x108e 5.3 wired for management (wfm) wired for management is an industry - wide initiative to increase overall manageabilit y and reduce total cost of ownership. wfm allows a server to be managed over a network. the system bios supports the system management bios reference specification, version 2.4 , to help higher - level instrumentation software meet the wired for management ba seline specification , revision 2.0 requirements. 5.3.1 pxe bios support the bios supports the efi pxe implementation as specified in chapter 15 of the extensible firmware interface reference specification , version 1.1. to utilize this, the user must load the ef i simple network protocol driver. the undi driver is specific to the network controller and must be included with the network card. the simple network protocol driver can be obtained from http://developer.intel.com/technology/framework. the bios supports legacy pxe option roms in legacy mode and includes the necessary pxe roms in the bios image for the onboard controllers. the legacy pxe rom is required to boot a non - efi operating system over the network. 5.4 system management bios (smbios) the bios provides s upport for the system management bios reference specification, version 2.4 , to create a standardized interface for manageable attributes that are expected to be supported by dmi - enabled computer systems. the bios provides this interface via data structures through which the system attributes are reported. using smbios, a system administrator can obtain the types, capabilities, operational status, installation date and other information about the server components. 5.5 security the bios provides several securit y features. this section describes the security features and operating model. 5.5.1 operating model the following table summarizes the operation of security features supported by the bios. free datasheet http://
platform management architecture intel? server board S3000PT tps 54 revision 1.3 table 37 . security features operating model mod e entry method / event entry criteria behavior exit criteria after exit password on boot power on / reset user password set and password on boot enabled in bios setup. secure boot disabled in bios setup. system halts for user password before scanning o ption roms. the system is not in secure mode. no mouse or keyboard input is accepted except the password. user password. administrator password. front control panel buttons are re - enabled. the server boots normally. boot sequence is determined by setup opt ions. 5.5.2 password protection the bios uses passwords to prevent unauthorized tampering with the server setup. both user and administrator passwords are supported by the bios. an administrator password must be entered in order to set the user password. the m aximum length of a password can be seven characters. the password cannot have characters other than alphanumeric (a - z, a - z, 0 - 9 ) . it is not case sensitive. once set, a password can be cleared by changing it to a null string. entering the user password will allow the user to modify the time, date, and user password. other setup fields can be modified only if the administrator password is entered. if only one password is set, this password is required to enter bios setup. the administrator has control over al l fields in bios setup, including the ability to clear the user password. if the user or administrator enters an incorrect password three times in a row during the boot sequence, the system is placed into a halt state. a system reset is required to exit ou t of the halt state. this feature makes it difficult to break the password by guessing at it. 5.5.3 password clear if the user and/or administrator password is lost or forgotten, both passwords may be cleared by moving the cmos c lear jumper into the clear posi tion. free datasheet http://
error reporting and handling intel? server board S3000PT tps revision 1.3 55 6. error reporting and handling this chapter defines the following error handling features: e error handling and logging e error messages and beep codes 6.1 error handling and logging this section defines how errors are handled by the system bios . in addition , error - logging techniques are described and beep codes for errors are defined. 6.1.1 error sources and types one of the major requirements of server management is to correctly and consistently handle system errors. system errors that can be enabled and disable d individually or as a group can be categorized as follows: e pci bus errors e memory single - and multi - bit errors e errors detected during post, logged as post errors the event list that would be logged is as follows: table 38 . event li st event name description when error is caught processor thermal trip of last boot processor thermal trip happened on last boot. post memory channel a multi - bit ecc error multi - bit ecc error happened on dimm channel a. post / runtime memory channel a si ngle - bit ecc error single - bit ecc error happened on dimm channel a. post / runtime memory channel b multi - bit ecc error multi - bit ecc error happened on dimm channel b. post / runtime memory channel b single - bit ecc error single - bit ecc error happened on dimm channel b. post / runtime cmos battery failure cmos battery failure or cmos clear jumper is set to clear cmos. post cmos checksum error cmos data corrupted post cmos time not set cmos time is not set post keyboard not found ps/2 kb is not found du ring post post memory size decrease memory size is decreased compared with last boot post chassis intrusion detected chassis is open post bad spd tolerance some fields of the dimm spd may not be supported, but could be tolerated by the memory reference code. post free datasheet http://
intel? server board S3000PT tps error reporting and handling 56 revision 1.3 pci perr error perr error happens on pci bus post / runtime pci serr error serr error happens on pci bus post / runtime 6.1.2 error logging via smi handler the smi handler is used to handle and log system level events. the smi handler pre - processe s all system errors, even those that are normally considered to generate an nmi. the smi handler log s the event to nvram . for example, the bios programs the hardware to generate a smi on a single - bit memory error and logs the error in the nvram in terms o f a smbios type 15 . after the bios finishes logging the error it will assert the nmi if needed. 6.1.2.1 pci bus error the pci bus defines two error pins, perr# and serr#. these are used for reporting pci parity errors and system errors, respectively. in the case of perr#, the pci bus master has the option to retry the offending transaction, or to report it using serr#. all other pci - related errors are reported by serr#. all pci - to - pci bridges are configured so that they generate a serr# on the primary interface wh enever there is a serr# on the secondary side . 6.1.2.2 pci express* errors all uncorrectable pci express* errors are logged as pci system errors and promoted to an nmi. all correctable pci express errors are not logged. 6.1.2.3 memory error s the hardware is programmed t o generate an smi on correctable data errors in the memory array. the smi handler records the error to the nvram . the uncorrectable errors may have corrupted the contents of smram. the smi handler will log the error to the nvram if the smram contents are s till valid. 6.1.3 smbios type 15 errors are logged to the nvram in terms of the smbios type 15 (system event log ) . r efer to the smbios specification , version 2.4 for more detail ed information. the format of the records is also defined in the following section. 6.1.4 logging format conventions the bios logs an error into the nvram area with the following record format, which is also defined in the smbios specification , version 2.3.4. free datasheet http://
error reporting and handling intel? server board S3000PT tps revision 1.3 57 table 39 . smbios type 15 event record f ormat offset name len gth description 00h event type byte specifies the type of event noted in an event - log entry as defined in table. 01h length byte specifies the byte length of the event record, including the records type and length fields. 02h year byte 03h month byte 04h day byte 05h hour byte 06h minute byte 07h second byte indicates the t ime when error is logged. 08h eventdata1 dword efi_status_code_type 0ch eventdata2 dword efi_status_code_value table 40 . event type definition ta ble value description used by this platform (y/n) 00h reserved n 01h single - bit ecc memory error y 02h multi - bit ecc memory error y 03h parity memory error n 04h bus time - out n 05h i/o channel check n 06h software nmi n 07h post memory resize n 08 h post error y 09h pci parity error y 0ah pci system error y 0bh cpu failure n 0ch eisa failsafe timer time - out n 0dh correctable memory log disabled n 0eh logging disabled for a specific event type C too many errors of the same type received in a sh ort period of time. free datasheet http://
intel? server board S3000PT tps error re porting and handling 58 revision 1.3 0fh reserved n 1 1 0h system limit exceeded (e.g. , voltage or temperature threshold exceeded) y 11h asynchronous hardware timer expired and issued a system reset n 12h system configuration information n 13h hard - disk information n 14h system reconfigured n 15h uncorrectable cpu - complex error n 16h log area reset/cleared y 17h system boot. if implemented, this log entry is guaranteed to be the first one written on any system boot. n 18h - 7fh unused , available for assignment by smb ios specification version 2.3.4. n 80h - feh available for system - and oem - specific assignments y ffh end - of - log. when an application searches through the event - log records, the end of the log is identified when a log record with this type is found . y fo r more information about the efi_status_code_type and efi_status_code_value definitions, refer to i ntel platform innovation framework for efi status codes specification , version 0.92. e rrors are also displayed on the bios setup screen under the server mana gement / view event log menu in the following format: eventname (times) time of occurrence eventname is followed by the number of occurrences of the same event. the time of occurrence is the last time the event occurred. 6.2 error messages and error codes th e system bios displays error messages on the video screen. before video initialization, beep codes inform the user of errors. post error codes are logged in the event log. the bios displays post error codes on the video monitor. 6.2.1 diagnostic leds during the system boot process, the bios executes several platform configuration processes, each of which is assigned a specific hex post code number. as each configuration routine is started, the bios will display the post code on the post code diagnostic leds foun d on the back edge of the server board. to assist in troubleshooting a system hang during the post process, the diagnostic leds can be used to identify the last post process to be executed. free datasheet http://
error reporting and handling intel? server board S3000PT tps revision 1.3 59 each post code is represented by a combination of colors from the four leds. the leds are capable of displaying three colors: green, red, and amber. the post codes are divided into an upper nibble and a lower nibble. each bit in the upper nibble is represented by a red led and each bit in the lower nibble is represented by a green led. if both bits are set in the upper and lower nibbles then both red and green leds are lit, resulting in an amber color. if both bits are clear, then the led is off. in the below example, the bios sends a value of ac h to the diagnostic led de coder. the leds are decoded as follows: red bits = 10 10 b = a h green bits = 1100 b = c h since the red bits correspond to the upper nibble and the green bits correspond to the lower nibble, the two are concatenated to be ac h. table 41 . post progress code led example 8h 4h 2h 1h leds red green red green red green red green ac h 1 1 0 1 1 0 0 0 result amber green red off msb lsb figure 26 . location of diagnostic leds on server board free datasheet http://
intel? server b oard S3000PT tps error reporting and handling 60 revision 1.3 6.2.2 post code checkpoi nts table 42 . post code checkpoints diagnostic led decoder g=green, r=red, a=amber checkpoint msb lsb description host processor 0x10h off off off r power - on initialization of the host processor (bootstrap processor) 0x1 1h off off off a host processor cache initialization (including ap) 0x12h off off g r starting application processor initialization 0x13h off off g a smm initialization chipset 0x21h off off r g initializing a chipset component memory 0x22h off off a off reading configuration data from memory (spd on dimm) 0x23h off off a g detecting presence of memory 0x24h off g r off programming timing parameters in the memory controller 0x25h off g r g configuring memory parameters in the memory controller 0x2 6h off g a off optimizing memory controller settings 0x27h off g a g initializing memory, such as ecc init 0x28h g off r off testing memory pci bus 0x50h off r off r enumerating pci busses 0x51h off r off a allocating resources to pci busses 0x52h of f r g r hot plug pci controller initialization 0x53h off r g a reserved for pci bus 0x54h off a off r reserved for pci bus 0x55h off a off a reserved for pci bus 0x56h off a g r reserved for pci bus 0x57h off a g a reserved for pci bus usb 0x58h g r off r resetting usb bus 0x59h g r off a reserved for usb devices ata / atapi / sata 0x5ah g r g r begin pata / sata bus initialization 0x5bh g r g a reserved for ata smbus 0x5ch g a off r resetting smbus 0x5dh g a off a reserved for smbus loca l console 0x70h off r r r resetting the video controller (vga) 0x71h off r r a disabling the video controller (vga) 0x72h off r a r enabling the video controller (vga) remote console 0x78h g r r r resetting the console controller free datasheet http://
error reporting and handling intel? server board S3000PT tps revision 1.3 61 diagnostic led decoder g=green, r=red, a=amber checkpoint msb lsb description 0x79h g r r a disabl ing the console controller 0x7ah g r a r enabling the console controller keyboard (ps2 or usb) 0x90h r off off r resetting the keyboard 0x91h r off off a disabling the keyboard 0x92h r off g r resetting the keyboard 0x93h r off g a enabling the keyb oard 0x94h r g off r clearing keyboard input buffer 0x95h r g off a instructing keyboard controller to run self test (ps2 only) mouse (ps2 or usb) 0x98h a off off r resetting the mouse 0x99h a off off a detecting the mouse 0x9ah a off g r detecting t he presence of mouse 0x9bh a off g a enabling the mouse fixed media 0xb0h r off r r resetting fixed media device 0xb1h r off r a disabling fixed media device 0xb2h r off a r detecting presence of a fixed media device (ide hard drive detection, etc.) 0xb3h r off a a enabling / configuring a fixed media device removable media 0xb8h a off r r resetting removable media device 0xb9h a off r a disabling removable media device 0xbah a off a r detecting presence of a removable media device (ide cdrom dete ction, etc.) 0xbch a g r r enabling / configuring a removable media device boot device selection 0xd0 r r off r trying boot device selection 0xd1 r r off a trying boot device selection 0xd2 r r g r trying boot device selection 0xd3 r r g a trying boot device selection 0xd4 r a off r trying boot device selection 0xd5 r a off a trying boot device selection 0xd6 r a g r trying boot device selection 0xd7 r a g a trying boot device selection 0xd8 a r off r trying boot device selection 0xd9 a r off a trying boot device selection 0xda a r g r trying boot device selection 0xdb a r g a trying boot device selection 0xdc a a off r trying boot device selection 0xde a a g r trying boot device selection 0xdf a a g a trying boot device select ion pre - efi initialization (pei) core 0xe0h r r r off started dispatching an peim free datasheet http://
intel? server board S3000PT tps error reporting and handling 62 revisio n 1.3 diagnostic led decoder g=green, r=red, a=amber checkpoint msb lsb description 0xe1h r r r g completed dispatching an peim 0xe2h r r a off initial memory found, configured, and installed correctly 0xe3h r r a g reserved for initialization module u se (peim) driver execution environment (dxe) core 0xe4h r a r off entered efi driver execution phase (dxe) 0xe5h r a r g reserved for dxe core use 0xe6h r a a off started connecting drivers 0xebh a r a g started dispatching a driver 0xe c h r a a off c ompleted dispatching a driver dxe drivers 0xe7h r a a g waiting for user input 0xe8h a r r off checking password 0xe9h a r r g entering bios setup 0xeah a r a off flash update 0xeeh a a a off calling int 19. one beep unless silent boot is enabled. 0 xefh a a a g reserved for dxe drivers use runtime phase / efi operating system boot 0xf4h r a r r entering sleep state 0xf5h r a r a exiting sleep state 0xf8h a r r r operating system has requested efi to close boot services ( exitbootservices ( ) has b een called) 0xf9h a r r a operating system has switched to virtual address mode ( setvirtualaddressmap ( ) has been called) 0xfah a r a r operating system has requested the system to reset (resetsystem () has been called) pre - efi initialization module (p eim) / recovery 0x30h off off r r crisis recovery has been initiated because of a user request 0x31h off off r a crisis recovery has been initiated by software (corrupt flash) 0x34h off g r r loading crisis recovery capsule 0x35h off g r a handing off control to the crisis recovery capsule 0x3fh g g a a unable to complete crisis recovery. 6.2.3 post error messages and handling whenever possible, the bios will output the current boot progress codes on the video screen. progress codes are 32 - bit quantities p lus optional data. the 32 - bit numbers include class, subclass, and operation information. the class and subclass fields point to the type of hardware that is being initialized. the operation field represents the specific initialization activity. based on t he data bit availability to display progress codes, a progress code can be customized to fit the data width. the higher the data bit, the higher the granularity of information that can be sent on the progress port. the progress codes may be reported by the system bios or option roms. the response column in the following table is divided into two types: free datasheet http://
error reporting and handling intel? server board S3000PT tps revision 1.3 63 e pause: the message is displayed in the error manager screen, an error may be logged to the nvram , and user input is required to continue. the user can take i mmediate corrective action or choose to continue booting. e halt: the message is displayed in the error manager screen, an error is logged to the nvram , and the system cannot boot unless the error is resolved. the user needs to replace the faulty part and re start the system. table 43 . post error messages and handling error code error message response log error cmos date / time not set pause y configuration cleared by jumper pause y configuration default loaded pause n password check failed halt n pci resource conflict pause n insufficient memory to shadow pci rom pause n processor thermal trip error on last boot pause y 6.2.4 post error beep codes the following table lists the post error beep codes. prior to system video initi alization, the bios uses these beep codes to inform users of error conditions. the beep code is followed by a user visible code on the post progress leds. table 44 . post error beep codes beeps error message post progress code descri ption 3 memory error system halted because a fatal error related to the memory was detected. 6.2.5 post error pause option in the event of post error(s) that are listed as "pause", the bios will enter the error manager and wait for the user to press an appro priate key before booting the operating system or entering bios setup. the user can override this option by setting "post error pause" to "disabled" in the bios setup main menu page. if the "post error pause" option is set to "disabled", the system will bo ot the operating system without user intervention. the default value is set to "enabled". free datasheet http://
intel? server board S3000PT tps connectors and jumper blocks 64 revision 1.3 7. connectors and jumper blocks 7.1 power connectors the power supply connection is supplied to the system through the 18 - pin connector. the following table defines the pin - outs of the connector. table 45 . power connector pin - out ( j3k2 ) pin signal 18 awg color pin signal 18 awg color 1* +3.3vdc orange 1 0 +3.3vdc orange 3.3v rs orange (24awg) 1 1 - 12vdc blue 2 com black 1 2 com black 3* com black 1 3 pson# green com rs black (24awg) 1 4 +5vdc red 4* +5vdc red 1 5 pwr_ok gray 5v rs red (24awg) 1 6 com black 5 5 vsb purple 17 com black 6 com black 18 +12v 3 yellow 7 com black 8 +12v 1 yellow 9 +12v2 yellow 7.2 smbus header table 46 . smbus header pin - out ( j1a1 ) pin signal name description 1 smb_data_ main data line 2 gnd ground 3 smb_clk_ main clock line free datasheet http://
connectors and jumper blocks intel? server board S3000PT tps revision 1.3 65 7.3 front panel connector a 14 - pin header is provided to support a system front panel. the header contains reset, nm i, power control buttons, and led indicators . the following table details the pin - out of this header. table 47 . front panel 14 - pin header pin - out ( j4k3 ) signal name pin signal name pin power led anode 1 nic1 activity led anode 2 p ower led cathode 3 nic1 activity led cathode 4 hd d activity led anode 5 nic2 activity led anode 6 hd d activity led cathode 7 nic2 activity led cathode 8 power switch 9 reset switch 10 power switch(gnd) 11 reset switch ( gnd) 12 key (pin removed) 13 nc 14 note: nc (no connect) 7.4 i/o connectors 7.4.1 vga connector the following table details the pin - out of the vga connector. table 48 . vga connector pin - out ( j4a1 ) signal name pin signal name pin red 1 fused vcc ( +5v) 9 green 2 gnd 10 b lue 3 nc 11 nc 4 ddcdat 12 gnd 5 hsy 13 gnd 6 vsy 14 gnd 7 ddcclk 15 gnd 8 note: nc (no connect) free datasheet http://
intel? server board S3000PT tps connectors and jumper blocks 66 revision 1.3 7.4.2 nic connectors the intel? server board S3000PT supports two nic rj - 45 connectors. the following tables detail the pin - out of the connector s . table 49 . nic1 - intel? 82573e (10/100/1000) connector pin - out ( ja2a1 ) signal name pin signal name pin p2v5_nic1 9 nic1_mdi3_dp 16 nic1_mdi0_dp 10 nic1_mdi3_dn 17 nic1_mdi0_dn 11 gnd 18 nic1_mdi1_dp 12 nic1_link_1_n 19 nic1_mdi1_dn 13 p3 v3_aux 20 nic1_mdi2_dp 14 nic1_link_0_n 21 nic1_mdi2_dn 15 nic1_link_2_n 22 table 50 . nic2 - intel? 82 573v ( 10/100/1000) connector pin - out ( ja2a2 ) signal name pin signal name pin gnd 1 nic2_mdi 0 _dp 9 p2v5_nic2_rc 2 nic2_mdi 0 _d n 10 nic2_mdi3_dp 3 nic2_link_2_n d1 nic2_mdi3_d n 4 nic2_link_0_n d2 nic2_mdi 2 _dp 5 p3v3_aux d3 nic2_mdi 2 _d n 6 nic2_link_1_n d4 nic2_mdi 1 _dp 7 nic2_mdi 1 _d n 8 7.4.3 sata connectors the intel? ich7r controller integr ates a sata controller with two sata p orts. the pin - out for these four connectors is defined in the following table . table 51 . sata connector pin - out ( j1c2, j1c3 ) pin signal name 1 gnd 2 sata0_tx_p 3 sata0_tx_n 4 gnd 5 sata0_rx_n 6 sata0_rx_p 7 gnd free datasheet http://
connectors and jumper blocks intel? server board S3000PT tps revision 1.3 67 7.4.4 serial port c onnectors one full y - functional serial port and one tx/rx only serial port is provided on the intel? server board S3000PT . a standard, external db9 serial connector is located on the back edge of the server board to supply a serial a interface. an internal 3 - pin header supplies a serial b interface. table 52 . external db9 serial a port pin - out (j 3 a1) signal name pin signal name pin dcd 1 dsr 6 rxd 2 rts 7 txd 3 cts 8 dtr 4 ri 9 gnd 5 table 53 . internal 9 - pin serial b port pin - out ( j2b1 ) signal name pin rx d 1 gnd 2 tx d 3 7.4.5 usb connector the following table provides the pin - out for the dual external usb connectors. this connector is combined with an rj - 45 (connected to nic1 signals). table 54 . usb connectors pin - out ( ja2a1 ) pin signal name 1 p5v_usb_bp_mj 2 usb_back5_r_dn 3 usb_back5_r_dp 4 gnd 5 p5v_usb_bp_mj 6 usb_back4_r_dn 7 usb_back4_r_dp 8 gnd a header on the server board provides an option to support two addition al usb ports . the pin - out of the header is detailed in the following table. free datasheet http://
intel? server board S3000PT tps connectors and jumper blocks 68 revision 1.3 table 55 . optional usb connection header pin - out ( j1c1 ) signal name pin signal name pin nc 1 key (pin removed) 2 gnd 3 gnd 4 usb_front1_inductor_dp 5 usb _front 2 _inductor_dp 6 usb_front1_inductor_dn 7 usb_front 2 _inductor_d n 8 usb_fnt_pwr ( fused vcc , +5v /w over current monitor of port 1 ) 9 usb_fnt_pwr ( fused vcc , +5v /w over current monitor of port 1 ) 10 7.5 fan headers there are three general - purpose (syst em) fan headers ( j 3k1 , j4k2, j4k1 ) . these fan headers have the sam e pin - out and are detailed in the following table . table 56 . 8 - pin fan headers pin - out ( j 3k1,j4k2,j4k1 ) pin signal name type description 1 ground power ground is the power supply ground 2 fan power power fan power +12vdc 3 fan tach 1 sense fan_tach signal is connected to the smsc* sch5027 or sch5017 to monitor the fan speed. 4 pwm 1 control pulse width modulation C fan speed control signal 5 ground power ground is t he power supply ground 6 fan power power fan power +12vdc 7 fan tach 2 sense fan_tach signal is connected to the smsc* sch5027 or sch5017 to monitor the fan speed. it use a different tach input other than tach1. 8 pwm 1 control pulse width modulation C f an speed control signal . it used the same pwm signal as pwm1 free datasheet http://
connectors and jumper blocks intel? server board s3000 pt tps revision 1.3 69 7.6 miscellaneous headers and connectors 7.6.1 back panel i/o connectors figure 27 . back panel i/o connections (not to scale) 7.6.2 non - standard connecto r information ref erence des ignator item desc ription mfr name mfr part number wieson technologies co., ltd g2100c888 - 060h j4k3 front panel connector foxconn electronics, inc. hc2907u - u4 j3k1, j4k1, j4k2 8pin fan connector molex connector co rporation 53047 - 0810 j3k2 horizontal power connector molex connector corporation 15 - 24 - 9184 j3k2 vertical power connector lotes aba - pow - 010 - t08 - k tyco electronics corporation 1470004 - 1 foxconn electronics, inc. hc3905u - p3 wieson technologies co., ltd 2100c888 - 045 foxconn electronics, inc. hc2905u - p3 wieson technologies co., ltd 2100c888 - 045g1 j1c1 internal usb connector wieson technologies co., ltd g2100c888 - 045h j1a1 smbus connector wieson technologies co., ltd g2420c888 - 005h foxconn electronics, inc. ld1807f - s15p wieson technologies co., ltd 1212c888 - 009g wieson technologies co., ltd g1212c888 - 009 j1c2, j1c3 internal sata connector wieson technologies co., ltd g1212c888 - 014 free datasheet http://
intel? server board S3000PT tps connectors and jumper blocks 70 revision 1.3 foxconn electronics, inc. hf2704e - m1 molex connector corporation 47053 - 1000 tyco electronics corporation 1470947 - 1 wieson technologies co., ltd 2366c888 - 007 wieson technologies co., ltd 2366c888 - 007g1 j2h1 4pin aux fan connector wieson technologies co., ltd g2366c888 - 007h table 57 . non - standard connector information 7.6.3 post code leds four post code leds display post code progression activities using hexadecimal format, read from the least significant bit to the most significant bit . these leds are not visible from the rear i/o panel. 7.7 jumper blocks this section describes configuration jumper options on the intel? server board S3000PT . 7.7.1.1 clear cmos and nic1 firmware u pdate and system maintenance mode jumpers both the cmos clear and th e nic1 firmware update jumper consist of 3 - pin headers ( cmos clear = j1b1 , nic1 fw update = j1b2 ) located just behind the dimm slots and near the board edge . the intel? server board S3000PT provides two 3 - pin jumper blocks that are used to perform clearing of nvram and enabling of nic1 firmwar e update options. the factory defaults are set to normal mode for each function. the following tables describe each jumper option. table 58 . cmos clear jumper options ( j1b1 ) free datasheet http://
connectors and jumper blocks intel ? server board S3000PT tps revision 1.3 71 table 59 . nic1 firmware update jumper opt ions ( j1b 2 ) table 60 . system maintenance mode jumper options ( j1b 3 ) name pin C pin function description normal 1 - 2 normal ope ration jumper in normal position allows system to successfully post and boot to operating system environment. bios settings are maintained intact. cmos clear 2 - 3 clears cmos (nvram) jumper in clear position initiates clear of nvram following post. system message confirms success of cmos clear operation. this setting enforces default bios settings, which can be changed by entering setup via f2, then exiting setup via f10 and saving changes. name pin C pin function description normal 1 - 2 normal operation jumper in normal position allows system to successfully post and boot to operating system environment. bios settings are maintained intact. recover 2 - 3 disable nic1 firmware upda te protection jumper in recover position disables nvram protection of nic1. it allows the user to update intel? amt firmware for nic1. name pin C pin function description normal 1 - 2 normal operation allows normal system operation with correct bios settings. system will post normally. maintenance mode 2 - 3 maintenance mode intel ? amt setting/password reset . free datasheet http://
intel? server board S3000PT tps absolute maximum ratings 72 revision 1.3 8. absolute maximum ratings operating the board at conditions beyond those shown in the following table may cause permanent damage to the system. the table is provided for stress testing purposes only. exposure to absolute maximum rating conditions for extended periods may affect system reliability. table 61 . absolute maximum ratings operating temperature 5 e c to 50 e c 1 storage temperature - 55 e c to +150 e c voltage on any signal with respect to ground - 0.3 v to vdd + 0.3v 2 3.3 v supply voltage with respect to ground - 0.3 v to 3.63 v 5 v supp ly voltage with respect to ground - 0.3 v to 5.5 v notes : 1. chassis design must provide proper airflow to avoid exceeding the processor maximum case temperature. 2. vdd means supply voltage for the device . 8.1 mean time between failures (mtbf) test results this s ection provides results of mtbf testing conducted by an intel testing facility. mtbf is a standard measure for the reliability and performance of the board under extreme working conditions. for the intel? server board S3000PT , the mtbf was measured at 20k hours at 40 degrees centigrade. free datasheet http://
design and environmental specifications intel? server board S3000PT tps revision 1.3 73 9. design and environmental specifications 9.1 p ower budget the following table shows the power consumed on each supply line for the intel ? server board S3000PT that is configured with one processor ( 130 w max). this configuration includes four 1 - gb ddr2 dimms stacked burst at 90% max. the numbers provided in the table should be used for reference purposes only. different hardware configurations will produce different numbers. the numbers in the table reflect a common usage model op erating at higher than average stress levels. table 62 . the board power budget power supply rail voltages watts amps units functional unit utilization power 3.3v 5.v 12.v 12v vrm - 12v 5vsb server board input totals 260 w 2.9 13.9 2.8 12.2 0.05 1.54 amps server board discrete totals 50% 45 w 2.9 0.5 0.00 0.00 0.00 0.04 amps server board converters efficiency 4 0 w 0.00 13.4 0.00 12.2 0.00 1.5 amps server board config totals 175.8 w 0.00 0.00 2.8 0.00 0.05 0.00 amps system comp onents 29 w 0.00 2.8 3.6 0.00 0.00 0.00 amps system totals 291 w 2.9 15.2 4.7 12.2 0.05 1.54 amps 3.3v / 5v combined power power supply requirements C 1u 300w 14a 18a max 12v+ 12v vrm 0.5a 2a 350w peak 3.3v/5v combined power 100w 1amin 1amin 2amin 2amin 0amin 1amin 9.2 product regulatory compliance 9.2.1 product safety compliance the intel ? server board S3000PT complies with the following safety requirements: e ul60950 C csa 60950(usa / canada) e en60950 (europe) e iec60950 (international) e cb certificate and report, iec60950 (report to include all country national deviations) e ce - low voltage directive 73/23/eee (europe) free datasheet http://
intel? server board S3000PT tps design and environmental specifications 74 revision 1.3 9.2.2 product emc compliance C class a compliance note : legally the product is required to comply with class a emission requirem ents as it is intended for a commercial type market place. intel targets 10db margin to class a limits . the intel? server board S3000PT has been tested and verified to comply with the following electromagnetic compatibility (emc) regulations when installed in a compatible intel ? host system. for information on compatible host system(s), refer to intels server builder web site or contact your local intel representative. e fcc /ices - 003 - emissions (usa/canada) verification e cispr 22 C emissions (international) e en55022 - emissions (europe) e ce C emc directive 89/336/eec (europe) e as/nzs 3548 emissions (australia / new zealand) 9.2.3 certifications / registrations / declarations e ul certification (us/canada) e cb certification (international) e ce declaration of conformity ( cenelec europe) e fcc/ices - 003 class a attestation (usa/canada) e c - tick declaration of conformity (australia) e med declaration of conformity (new zealand) free datasheet http://
design and environmental specifications intel? server board S3000PT tps revision 1.3 75 9.2.4 product regulatory compliance markings this product is marked with the following product certification markings. table 63 . product certification markings 9.3 electromagnetic compatibility notices 9.3.1 ind ustry canada (ices - 003) cet appareil numrique respecte les limites bruits radiolectriques applicables aux appareils numriques de classe a prescrites dans la norme sur le matriel brouilleur: apparelis numriques, nmb - 003 dictee par le ministre canadi an des communications. this digital apparatus does not exceed the class a limits for radio noise emissions from digital apparatus set out in the interference - causing equipment standard entitled: digital apparatus, ices - 003 of the canadian department of com munications. regulatory compliance region marking ul mark usa/canada e139761 ce mark europe canada emc mark canada canada ices - 003 class a c - tick mark australia country of origin ex porting requirements made in xxxxx (provided by label not silkscreen) model designation regulatory identification board pb number will be used for the model number pb free marking environmental requirements free datasheet http://
intel? server board S3000PT tps design and envi ronmental specifications 76 revision 1.3 9.3.2 europe (ce declaration of conformity) this product h as been tested in accordance to , and complies with the low voltage directive ( 73/23/eec) and emc directive (89/336/eec). the product has been marked with the ce mark to illustrate its complia nce. 9.3.3 australia / new zealand this product has been tested and complies with as/nzs 3548. the product has been marked with the c - tick mark to illustrate compliance. 9.4 restriction of hazardous substances (rohs) intel has a system in place to restrict the use o f banned substances in accordance with the european directive 2002/95/ec. compliance is based on declaration that materials banned in the rohs directive are either (1) below all applicable substance threshold limits or (2) an approved/pending rohs exemptio n applies. note: rohs implementing details are not fully defined and may change. threshold limits and banned substances are noted below. e quantity limit of 0.1% by mass (1000 ppm) for: o lead o mercury o hexavalent chromium o polybrominated biphenyls dipheny ethe rs (pbde) e quantity limit of 0.01% by mass (100 ppm) for: o cadmium 9.5 calculated mean time between failures (mtbf) the mtbf (mean time between failures) for the intel? server board S3000PT as configured from the factory is shown in the following table . table 64 . calculated mtbf data operating temperature calculated mtbf value 3 0 degrees c elsius 205 ,000 hours 40 degrees celsius 121 ,000 hours free datasheet http://
design and environmental specifications intel? server board S3000PT tps revision 1.3 77 9.6 mechanical specifications the following figure shows a mechanical drawing of the intel? server board S3000PT . figure 28 . intel? server board S3000PT mechanical drawing free datasheet http://
intel? server board S3000PT tps hardware monitoring 78 revision 1 .3 10. hardware monitoring 10.1 monitored components the intel? server board S3000PT has a n smsc* sch5027 or sch5017 super io controller with i ntegrated hardware mo nitoring function . it provide s basic server hardware monitoring which alerts a system administrator if a hardware problem occurs on the board. it also has implemented some fan speed control/monitor pins. the following table provides a list of monitored hea ders and sensors on the board. table 65 . monitored components item description voltage vcc p _in (pin # 127 ) monitors processor voltage v1_in (pin # 1 ) monitors +12vin for system +12v supply v2_in (pin # 2 ) monitors + 5 vin for sys tem + 5 v supply +2.5vtr_in (pin # 128 ) monitors 1. 5v core power vbat (pin # 32 ) monitors battery power vtr1 ( pin # 4) monitors + 3.3 vin for system + 3.3 v supply hvtr ( pin # 122) monitors + 3.3 v _stby for system + 3.3 v standby supply fan speed pwm1 (pin # 111 ) controls system fan 3 ( j4k1) pwm2 (pin # 110 ) controls system fan 2 ( j4k2) pwm3 (pin # 109 ) controls system fan 1 ( j3k1) tach1 (pin # 115 ) monitor s system fan 1 ( j3k1) tach2 (pin # 114 ) monitor s system fan 3 ( j4k1) tach 3 (pin # 113 ) monito r s system fan 1 ( j3k1) tach 4 (pin # 112 ) monitor s system fan 2 ( j4k2) tach a (pin # 79 ) monitor s system fan 2 ( j4k2) tach b (pin # 77 ) monitor s system fan 3 ( j4k1) smsc* sch5027 or sch5017 embedded temperature sensor peci ( pin # 119 ) mo nitors processor temperature through peci interface 1 remote1n/p( pin # 125/6) monitors processor temperature temperature remote2n/p( pin # 123/4) monitors system inlet air temperature through sensor ( q4k3) near fp connector 1 note: the smsc* sch5017 does not have a peci interface . free datasheet http://
hardware monitoring intel? server board S3000PT t ps revision 1.3 79 10.1.1 fan speed control figure 29 . fan speed control block diagram free datasheet http://
glossary intel? server boa rd S3000PT tps 80 revision 1.3 glossary this appendix contains important terms used in the preceding chapters. for ease of us e, numeric entries are listed first (e.g., 82460gx) with alpha entries following (e.g., agp 4x). acronyms are then entered in their respective place, with non - acronyms following. term definition acpi advanced configuration and power interface ansi am erican national standards institute ap application processor asic application specific integrated circuit asr asynchronous reset bga ball - grid array bios basic input/output system byte 8 - bit quantity. cmos in terms of this specification, this descri bes the pc - at compatible region of battery - backed 128 bytes of memory, which normally resides on the server board. dcd data carrier detect dma direct memory access dmtf distributed management task force ecc error correcting code emc electromagnetic co mpatibility eps external product specification escd extended system configuration data fdc floppy disk controller fifo first - in, first - out fru field replaceable unit gb 1024 mb . gpio general purpose i/o guid globally unique id hz hertz (1 cycle/s econd) hdg hardware design guide i 2 c inter - integrated circuit bus ia intel? architecture icmb intelligent chassis management bus ierr internal error imb inter module bus ip internet protocol irq interrupt request itp in - target probe kb 1024 bytes kcs keyboard controller style lan local area network lba logical block address lcd liquid crystal display lpc low pin count free datasheet http://
intel? server board S3000PT tps glossary revision 1.3 81 term definition lsb least significant bit mb 1024 kb mbe multi - bit error ms milliseconds msb most significant bit mtbf mean time between failures mux multiplexor nic network interface card nmi non - maskable interrupt oem original equipment manufacturer ohm unit of electrical resistance pbga pin ball grid array perr parity error pio programmable i/o pmb private management bus pmc p latform management controller pme power management event pnp plug and play post power - on self test pwm pulse - width modulator raidios raid i/o steering ram random access memory ri ring indicate risc reduced instruction set computing rmcp remote man agement control protocol rom read only memory rtc real time clock sbe single - bit error sci system configuration interrupt sdr sensor data record sdram synchronous dynamic ram sel system event log serirq serialized interrupt requests serr system e rror sm server management smi server management interrupt. smi is the highest priority non - maskable interrupt smm system management mode sms system management software snmp simple network management protocol spd serial presence detect ssi server st andards infrastructure tps technical product specification uart universal asynchronous receiver and transmitter usb universal serial bus vga video graphic adapter free datasheet http://
glossary intel? server board S3000PT tps 82 revision 1.3 term definition vid voltage identification vrm voltage regulator module word 16 - bit quantity zcr ze ro channel raid free datasheet http://
intel? server board S3000PT tps references revision 1.3 83 references e advanced configuration and power interface specification , revision 1.0b, february 1999, http://www.acpi.info/ e advanced configuration and power interface specification , revision 2.0, july 2 000, http://www.acpi.info/ e advanced configuration and power interface specification , revision 3.0, , http://www.acpi.info/ e bios boot specification version 1.01. compaq computer corporation, phoenix technologie ltd., intel corporation. 1996, http://www.phoenix.com/resources/specs - bbs101.pdf e el torito cd - rom boot specification , version 1.0, http://www.phoenix.com/resources/specs - cdrom.pdf e extensible firmware interface reference specification , version 1.1, http://www.intel.com/technology/e fi/index.htm e tiano efi shell eps , revision 0.10. intel corporation, 2002 e efi 1.1 shell commands specification , v0.3, available from: efi1.1shellcommands.pdf, efi sample implementation, revision 1.10.14.62, http://developer.intel.com/technology/efi/main_sample.htm e ia - 32e bios writer's guide , revision 0.5, intel corporation e platform management fru information storage definition v1.0, http://developer.intel.com/design/servers/ipmi e hardware design guide for microsoft windows 2000 server , version 3.0, http://www.microsoft.c om/whdc/system/platform/pcdesign/desguide/serverdg.mspx#esb e application note ap - 485: intel processor identification and the cpuid function , http://www.intel.com/design/xeon/applnots/241 618.htm e intelligent platform management bus specification , version 1.0, http://developer.intel.com/design/servers/ipmi/spec.htm e intelligent platform management interface specificat ion , version 1.5, http://developer.intel.com/design/servers/ipmi/spec.htm e intelligent platform management interface specification , version 2.0, http://developer.intel.com/design/servers/ipmi/spec.htm e multiprocessor specification , revision 1.4, may 1997 e microsoft headless design guidelines , http://www.microsoft.com/hwdev/platform/server/headless/default.asp e pci local bus specification, revision 3.0, http://www.pcisig.org/ e pci local bus specification , revision 2.2, http://www.pcisig.org/ free datasheet http://
references intel? server board S3000PT tps 84 revision 1.3 e pc i bios specification , revision 2.1, http://www.pcisig.org/ e pci to pci bridge specification , revision 1.1, http://www.pcisig.org/ e pci express base specification , revision 1.0a , http://www.pcisig.org/ e pci hot - plug specification , revision 1.1, http://www.pcisig.org/ e pci irq routing table specification , revision 1.0, microsoft corporation e plug and pl ay bios specification , revision 1.0a (relevant portions only), http://www.microsoft.com/whdc/system/pnppwr/pnp/default.mspx e sahalee baseboard management controller core external product specification for silverwood systems , intel corporation e system management bios reference specification, version 2.4, http://www.dmtf.org/standards/smbios e acpi static resource affinity table, v ersion 1.2, http://www.microsoft.com/whdc/hwdev/platform/proc/srat.mspx e sysid bios support interface requirement specification , version 1.2 e intel? platform innovation framework for efi firmware volume specification , revision 0.9, intel corporation, 2004, ftp://download.intel.com/technology/framework/docs/fv.pdf e universal host controller interface design guid e , http://developer.intel.com/design/usb/uhci11d.htm e universal serial bus revision 1.1 specification, http://www.usb.org/developers/docs e universal serial bus revision 2.0 specification, http://www.usb.org/developers/docs e wired for management baseline specification , revision 2.0, http://www.intel.com/labs/manage/wfm/wfmspecs.htm e dmtf systems standard groups definition free datasheet http://

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